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kuznia-rdzeni / coreblocks

RISC-V out-of-order core for education and research purposes
https://kuznia-rdzeni.github.io/coreblocks/
BSD 3-Clause "New" or "Revised" License
38 stars 16 forks source link

Support top-level signals in TransactionComponent #723

Closed piotro888 closed 2 months ago

piotro888 commented 4 months ago

TransactionComponent only supports connecting nested Signatures. It crashes when connecting plain signals (In/Out) at top level. Amaranth connect can be used at higher level to support both cases, it also iterates over sub-signatures internally

github-actions[bot] commented 4 months ago

Benchmarks summary

Performance benchmarks

aha-mont64 crc32 minver nettle-sha256 nsichneu slre statemate ud
0.417 0.513 0.337 0.655 0.361 0.29 0.326 0.431

You can view all the metrics here.

Synthesis benchmarks (basic)

Device utilisation: (ECP5) LUTs used as DFF: (ECP5) LUTs used as carry: (ECP5) LUTs used as ram: (ECP5) Max clock frequency (Fmax)
25503 5924 770 972 50

Synthesis benchmarks (full)

Device utilisation: (ECP5) LUTs used as DFF: (ECP5) LUTs used as carry: (ECP5) LUTs used as ram: (ECP5) Max clock frequency (Fmax)
32425 9177 1976 1152 38
github-actions[bot] commented 2 months ago

Benchmarks summary

Performance benchmarks

aha-mont64 crc32 minver nettle-sha256 nsichneu slre statemate ud
0.417 (0.000) 0.513 (0.000) 0.337 (0.000) 0.655 (0.000) 0.361 (0.000) 0.290 (0.000) 0.326 (0.000) 0.431 (0.000)

You can view all the metrics here.

Synthesis benchmarks (basic)

Device utilisation: (ECP5) LUTs used as DFF: (ECP5) LUTs used as carry: (ECP5) LUTs used as ram: (ECP5) Max clock frequency (Fmax)
▼ 24577 (-173) 5889 (0) ▼ 770 (-32) 972 (0) ▼ 50 (-2)

Synthesis benchmarks (full)

Device utilisation: (ECP5) LUTs used as DFF: (ECP5) LUTs used as carry: (ECP5) LUTs used as ram: (ECP5) Max clock frequency (Fmax)
▼ 37424 (-1576) 9142 (0) 1944 (0) 1152 (0) ▲ 42 (+1)