kuznia-rdzeni / coreblocks

RISC-V out-of-order core for education and research purposes
https://kuznia-rdzeni.github.io/coreblocks/
BSD 3-Clause "New" or "Revised" License
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Clean up `MemoryBank` #730

Closed tilk closed 1 week ago

tilk commented 1 week ago

This PR fixes something which bothered me for a long time. I couldn't wrap my head around why @lekcyjna123's MemoryBank implementation is so weird and complex. Finally, I understood the problem: in the version of Amaranth we are using, the read ports are transparent by default (!), and @lekcyjna123 basically tried to make non-transparent reads from a transparent read port.

What was changed: