Efficient register file implementation on FPGAs requires the use of block RAM, which is synchronous. Currently register reads are asynchronous: the register values are read during the RS insertion phase. Synchronous register reads could be implemented using a MemoryBank with reads initiated during RS selection and completed during RS insertion.
To materialize the gain, #734 needs to be implemented, as the register file has three ports - too much for a single block RAM.
Efficient register file implementation on FPGAs requires the use of block RAM, which is synchronous. Currently register reads are asynchronous: the register values are read during the RS insertion phase. Synchronous register reads could be implemented using a
MemoryBankwith reads initiated during RS selection and completed during RS insertion.To materialize the gain, #734 needs to be implemented, as the register file has three ports - too much for a single block RAM.