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kuznia-rdzeni / coreblocks

RISC-V out-of-order core for education and research purposes
https://kuznia-rdzeni.github.io/coreblocks/
BSD 3-Clause "New" or "Revised" License
38 stars 16 forks source link

Update Amaranth to before RFC 36 #738

Closed tilk closed 4 weeks ago

tilk commented 1 month ago

Mostly minor changes to type stubs. RFC 36 is for the async/await based testing, which is a major change, so I would like to work on it separately.

github-actions[bot] commented 1 month ago

Benchmarks summary

Performance benchmarks

aha-mont64 crc32 minver nettle-sha256 nsichneu slre statemate ud
0.417 0.513 0.337 0.655 0.361 0.29 0.326 0.431

You can view all the metrics here.

Synthesis benchmarks (basic)

Device utilisation: (ECP5) LUTs used as DFF: (ECP5) LUTs used as carry: (ECP5) LUTs used as ram: (ECP5) Max clock frequency (Fmax)
14589 6043 802 1068 57

Synthesis benchmarks (full)

Device utilisation: (ECP5) LUTs used as DFF: (ECP5) LUTs used as carry: (ECP5) LUTs used as ram: (ECP5) Max clock frequency (Fmax)
29262 9298 1790 1248 42
github-actions[bot] commented 4 weeks ago

Benchmarks summary

Performance benchmarks

aha-mont64 crc32 minver nettle-sha256 nsichneu slre statemate ud
0.417 (0.000) 0.513 (0.000) 0.337 (0.000) 0.655 (0.000) 0.361 (0.000) 0.290 (0.000) 0.326 (0.000) 0.431 (0.000)

You can view all the metrics here.

Synthesis benchmarks (basic)

Device utilisation: (ECP5) LUTs used as DFF: (ECP5) LUTs used as carry: (ECP5) LUTs used as ram: (ECP5) Max clock frequency (Fmax)
▼ 14776 (-794) 6043 (0) ▼ 802 (-32) 1068 (0) ▲ 53 (+1)

Synthesis benchmarks (full)

Device utilisation: (ECP5) LUTs used as DFF: (ECP5) LUTs used as carry: (ECP5) LUTs used as ram: (ECP5) Max clock frequency (Fmax)
▼ 24301 (-1019) 9298 (0) ▼ 1758 (-32) 1248 (0) ▼ 45 (-1)