Implement vectored interrupt mode in `mtvec`

kuznia-rdzeni / coreblocks

RISC-V out-of-order core for education and research purposes

https://kuznia-rdzeni.github.io/coreblocks/

BSD 3-Clause "New" or "Revised" License

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Closed piotro888 closed 1 week ago

piotro888 commented 4 weeks ago

Defined in 3.1.7. Machine Trap-Vector Base-Address Register

Currently only direct mode is supported, where all traps set pc to mtvec value. Vectored mode uses different pc offsets for trap cause codes

This is an optional feature.