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kuznia-rdzeni / coreblocks

RISC-V out-of-order core for education and research purposes
https://kuznia-rdzeni.github.io/coreblocks/
BSD 3-Clause "New" or "Revised" License
38 stars 16 forks source link

mtvec vectored mode #755

Closed kalinf closed 1 week ago

kalinf commented 2 weeks ago

Implement vectored interrupt mode in mtvec (issue #745)