Accept custom `CoreConfiguration` in `gen_verilog` script

kuznia-rdzeni / coreblocks

RISC-V out-of-order core for education and research purposes

https://kuznia-rdzeni.github.io/coreblocks/

BSD 3-Clause "New" or "Revised" License

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Accept custom `CoreConfiguration` in `gen_verilog` script #757

Open piotro888 opened 2 weeks ago

piotro888 commented 2 weeks ago

(from meeting?) It would be great to support reading custom CoreConfiguration derived configurations from external input file in gen_verilog script, so Coreblocks source wouldn't need to be modified to customize core.