Superscalar instruction decoding

kuznia-rdzeni / coreblocks

RISC-V out-of-order core for education and research purposes

https://kuznia-rdzeni.github.io/coreblocks/

BSD 3-Clause "New" or "Revised" License

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Open tilk opened 23 hours ago

tilk commented 23 hours ago

Modify the decoder stage so that it can decode multiple instructions in a single clock cycle. Also, to connect such decoder to the rest of the core:

Use WideFifo to reduce the amount of instructions between the fetcher and decoder.
Serialize the instructions going to the scheduler so that the current scalar scheduler can be used.