Closed kv-be closed 2 years ago
u_pulse_synchronizer : entity work.pulse_synchronizer port map( clk_1 => HSL_CLK, -- in std_logic; clk_2 => AXI_CLK, -- in std_logic; pulse_1 => line_ready_hsl, -- in std_logic; pulse_2 => line_ready_axi-- out std_logic; );
results in u_pulse_synchronizer : entity work.pulse_synchronizer port map( clk_1 => HSL_CLK, -- in std_logic; clk_2 => AXI_CLK, -- in std_logic; pulse_1 => line_ready_hsl, -- in std_logic; pulse_2 => line_ready_ax i-- out std_logic; );
solved in v1.0.1
kv-be
commented
2 years ago kv-be
commented
2 years ago
u_pulse_synchronizer : entity work.pulse_synchronizer port map( clk_1 => HSL_CLK, -- in std_logic; clk_2 => AXI_CLK, -- in std_logic; pulse_1 => line_ready_hsl, -- in std_logic; pulse_2 => line_ready_axi-- out std_logic; );
results in u_pulse_synchronizer : entity work.pulse_synchronizer port map( clk_1 => HSL_CLK, -- in std_logic; clk_2 => AXI_CLK, -- in std_logic; pulse_1 => line_ready_hsl, -- in std_logic; pulse_2 => line_ready_ax i-- out std_logic; );