elsif generate does 2 indents

[kv-be]

g_dut : if G_SENSOR = "CARDINAL1280" generate i_dut : entity work.tdi_read_control generic map( G_SENSOR => G_SENSOR ) port map( CLK => clk, -- Main Clock FSM_ERROR => fsm_error -- Asserted when FSM in undefined state ); elsif G_SENSOR = "CMV12K" generate i_dut_hs : entity work.tdi_read_control generic map( G_SENSOR => G_SENSOR ) port map( CLK => clk, -- Main Clock RST => rst, -- Main Reset FSM_ERROR => fsm_error -- Asserted when FSM in undefined state );

        i_dut_pan : entity work.tdi_read_control
        generic map(
              G_SENSOR  => G_SENSOR
        )
        port map(
              CLK       => clk,          -- Main Clock
              RST       => rst,          -- Main Reset
              FSM_ERROR => fsm_error_pan -- Asserted when FSM in undefined state
        );
  end generate g_dut;

[kv-be]

solved