kv-be / pretty-vhdl

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incorrect record alignment #3

Closed kv-be closed 2 years ago

kv-be commented 2 years ago

-- Configuration record to be assigned in the test harness. type t_dt_vip_pxl_stream_bfm_config is record id_for_bfm : t_msg_id; id_for_bfm_wait : t_msg_id; id_for_bfm_poll : t_msg_id; data_pattern : t_vip_pxl_stream_data_pattern; -- Insert all BFM config parameters here -- Example: -- max_wait_cycles : integer; -- max_wait_cycles_severity : t_alert_level; -- clock_period : time; end record;

when input in a different way, it is OK type t_dt_vip_pxl_stream_bfm_config is record id_for_bfm : t_msg_id; id_for_bfm_wait : t_msg_id; id_for_bfm_poll : t_msg_id; data_pattern : t_vip_pxl_stream_data_pattern; -- Insert all BFM config parameters here -- Example: -- max_wait_cycles : integer; -- max_wait_cycles_severity : t_alert_level; -- clock_period : time; end record;