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kv-be / pretty-vhdl

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multiline signal declaration #40

Closed kv-be closed 4 months ago

kv-be commented 4 months ago

signal a : std_logic_vector(C_VERY_LONG_CONSTRUCT downto C_ANOTHER_VERY_LONG_CONSTRUCTION);

signal a : std_logic_vector(C_VERY_LONG_CONSTRUCT downto C_ANOTHER_VERY_LONG_CONSTRUCTION ) := (

                       );
kv-be commented 4 months ago

solved