kv-be / pretty-vhdl

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gives a executable error #51

Closed kv-be closed 5 months ago

kv-be commented 5 months ago

-- Filename: cmv12k_anc_mgt.vhd

-- Copyright (c) 2014 Deltatec (www.deltatec.be)

-- This file is provided without any express or implied warranties, including, -- but not limited to, the implied warranties of merchantability and fitness -- for a particular purpose. It is not intended for use in life support -- appliances, devices, or systems. Use in such applications is expressly -- prohibited.--

-- Engineers: Koen Vanhoof (KV)

-- History: 19/06/2016 (KV) : Creation of this file -- 14/01/2021 (KV) : Updated for the CSIMBA project

-- Description: -- This block extracts all information which is variable for each frame and needs -- to be included in the image meta data (ancillary data or ANC data). -- To get the data, the block monitors -- - what is sent to the SPI block and decodes this data to extract the sensor settings -- - the internal register contents (which are all inputs) and extracts the data needed -- - the temperature whenever it is ready

-- Notes:


-- LIBRARY --

library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all;

library dt; use dt.dt_num_utils_pkg.all;

use WORK.cmv12k_pkg.all; use WORk.cmv12k_anc_pkg.all;


-- ENTITY --

-- we need : -- texposure -- image_size -- sensor temperature -- frame_type -- cropping_start
-- cropping_size -- binning enable.

-- time : std_logic_vector(63 downto 0); -- 64 bit CDC format -- image_size : std_logic_vector(11 downto 0); -- size in bytes -- sensorTemp : std_logic_vector(15 downto 0); -- -- frame_type : std_logic; -- HS or PAN -- colStart : std_logic_vector(6 downto 0); -- in 32 bit increments: only 64 bit increments needed in final ANC, but 32 bit increments needed in IP -- imageWidth : std_logic_vector(7 downto 0); -- in 32 bit increments -- binning_en : std_logic; -- when 1, 2x2 binning is enabled.

entity cmv12k_anc_mgt is port ( CLK : in std_logic; -- system clk RST : in std_logic; -- reset

  HS_PLUS_PAN : in std_logic;
  MUTE_NEXT_PAN : in std_logic;

  CONFIG_INDEX                  : in  std_logic_vector;               -- active configuration
  SET_VAR_ROI                   : in  std_logic;                      -- pulse when the ROI's are written to the sensor
  VAR_ROI_DONE                  : in  std_logic;                      -- goes high when writing the ROI's is done
  SENSOR_REGISTER               : in  std_logic_vector;               -- sensor register written
  SENSOR_DATA                   : in  std_logic_vector;               -- parallel write SPI data to send to the sensor
  SENSOR_DATA_VAL               : in  std_logic;                      -- enable pulse when the data is valid

  INT_REGS_VAL                  : in  std_logic;                      -- pulse when the internal registers below can be sampled
  EXPOSURE_TIME_ONE             : in  std_logic_vector;               -- even exposure
  FRAME_TIME                    : in  std_logic_vector;               -- frame time
  IMAGE_PROC_CFG                : in  std_logic_vector;               -- all the settings for the image processing
  IMAGE_HEIGHT                  : out std_logic_vector(11 downto 0);  -- total size of the image. Needed to path the temperature readout.

  TIME_STAMP                    : in  std_logic_vector;               -- time stamp of the start of the integration
  TIME_STAMP_VAL                : in  std_logic;                      -- valid pulse for the above

  SENSOR_TEMP                   : in  std_logic_vector;               -- sensor temperature as readout from the sensor
  SENSOR_TEMP_VAL               : in  std_logic;                      -- valid pulse for the above
  ANC_INFO_READY                : in  std_logic;                      -- pulses when all ANC data is ready to be written to FIFO
  ANC_DATA_VAL                  : out std_logic;                      -- high when the ANC data can be written to the memory
  ANC_ID                        : out std_logic_vector;               -- ANC ID of the ANC output.
  ANC_DATA                      : out anc_data_t;                     -- packed ANC data, ready to interface axi_requester

); end cmv12k_anc_mgt;


-- ARCHITECTURE --

architecture rtl of cmv12k_anc_mgt is


-- TYPE --


-- CONSTANT --

constant c_FIXED_CONFIG : integer := 0; constant c_VAR_CONFIG : integer := 1; constant c_VAR_ROI : integer := 2;

-- addresses of the sensor registers needed for the ANC data constant c_IMAGE_FLIP_OFFSET : integer := 69; constant c_BIT_MODE_OFFSET : integer := 118; constant c_TEST_PAT_OFFSET : integer := 122; constant c_BLACK_REF_EN_OFFSET : integer := 89; constant c_INTERLEAVED_READOUT_OFFSET : integer := 70; constant c_PGA_OFFSET : integer := 115; constant c_DIG_GAIN_OFFSET : integer := 117; constant c_ROI_HEIGHT : integer := 1; constant c_ROI_START_0 : integer := 2; constant c_ROI_START_1 : integer := 3; constant c_ROI_START_2 : integer := 4; constant c_ROI_START_3 : integer := 5; constant c_ROI_START_4 : integer := 6; constant c_ROI_START_5 : integer := 7; constant c_ROI_START_6 : integer := 8; constant c_ROI_START_7 : integer := 9; constant c_ROI_START_8 : integer := 10; constant c_ROI_START_9 : integer := 11; constant c_ROI_SIZE_0 : integer := 34; constant c_ROI_SIZE_1 : integer := 35; constant c_ROI_SIZE_2 : integer := 36; constant c_ROI_SIZE_3 : integer := 37; constant c_ROI_SIZE_4 : integer := 38; constant c_ROI_SIZE_5 : integer := 39; constant c_ROI_SIZE_6 : integer := 40; constant c_ROI_SIZE_7 : integer := 41; constant c_ROI_SIZE_8 : integer := 42; constant c_ROI_SIZE_9 : integer := 43;

-- bit definitions of the sensor configuration bits in the sensor registers constant c_SENSOR_BLACK_REF : integer := 15; constant c_SENSOR_TEST_PAT : integer := 1; constant c_SENSOR_TRAINING_PAT : std_logic_vector(11 downto 0) := (others => '0'); constant c_SENSOR_INTERLEAVED_READOUT : integer := 1; constant c_SENSOR_PGA_GAIN : std_logic_vector(2 downto 0) := (others => '0'); constant c_SENSOR_PGA_DIV : integer := 3; constant c_SENSOR_DIG_GAIN : std_logic_vector(4 downto 0) := (others => '0'); constant c_SENSOR_START : std_logic_vector(11 downto 0) := (others => '0'); constant c_SENSOR_SIZE : std_logic_vector(11 downto 0) := (others => '0'); constant c_SENSOR_HEIGHT : std_logic_vector(11 downto 0) := (others => '0');


-- SIGNAL --

signal AncDataVal : std_logic; --! signal CfgCurrent : anc_data_t; signal CfgNext : anc_data_t; signal Ongoing : std_logic_vector(0 downto 0); signal AncId : unsigned(4 downto 0);

-- ATTRIBUTE --

attribute mark_debug : string; attribute mark_debug of CfgCurrent : signal is "TRUE"; attribute mark_debug of CfgNext : signal is "TRUE"; attribute mark_debug of ANC_DATA : signal is "TRUE";


-- BEGIN --

begin process (CLK, RST) variable Ongoing_v : std_logic_vector(Ongoing'range); variable Done_v : std_logic_vector(Ongoing'range); variable StartPulses_v : std_logic_vector(Ongoing'range); begin if rising_edge(CLK) then if (RST = '1') then CfgCurrent <= C_ANC_DATA_ZEROS; CfgNext <= C_ANC_DATA_ZEROS; Ongoing <= (others => '0'); AncDataVal <= '0'; AncId <= (others => '1'); else StartPulses_v := SET_VAR_ROI; Done_v := VAR_ROI_DONE; Ongoing_v := (others => '0'); for i in StartPulses_v'range loop if StartPulses_v(i) = '1' then Ongoing_v(i) := '1'; elsif Done_v(i) = '1' then Ongoing_v(i) := '0'; else Ongoing_v(i) := Ongoing(i); end if; Ongoing(i) <= Ongoing_v(i); end loop;

        -- Monitor the writes to the SPI memory. Depending on which address is written, the write data is copied into the corresponding 
        -- ANC fields.
        if (Ongoing_v(c_VAR_ROI) = '1') and SENSOR_DATA_VAL = '1' then
           case to_integer(unsigned(SENSOR_REGISTER)) is
                 -- the general settings
              when c_ROI_HEIGHT => IMAGE_HEIGHT <= SENSOR_DATA(c_SENSOR_SIZE'range);
              when others       => null;
           end case;
        end if;

        if INT_REGS_VAL = '1' then
           -- when the internal register inputs are valid, store them in the next field, since they
           -- they are read BEFORE the exposure is started (to know which exposure time to use)
           CfgNext.frame_type                           <= IMAGE_PROC_CFG(C_PL_VNIR_VAR_IMG_CFG_CFG_HS_PAN'high);
           CfgNext.binning_en                           <= IMAGE_PROC_CFG(C_PL_VNIR_VAR_IMG_CFG_CFG_BINNING_EN'high);
           CfgNext.colStart                             <= IMAGE_PROC_CFG(C_PL_VNIR_VAR_IMG_CFG_CFG_CROP_START'range);
           CfgNext.image_size                           <= IMAGE_SIZE;
           -- the image width has an additional bit for the cropping block to allow setting the width to 128 (==8bit)
           CfgNext.imageWidth(CfgNext.imageWidth'range) <= '0' & IMAGE_PROC_CFG(C_PL_VNIR_VAR_IMG_CFG_CFG_CROP_LENGTH'range);

           if IMAGE_PROC_CFG(C_PL_VNIR_VAR_IMG_CFG_CFG_CROP_LENGTH'range) = zeros(C_PL_VNIR_VAR_IMG_CFG_CFG_CROP_LENGTH'length) then
              CfgNext.imageWidth(CfgNext.imageWidth'high) <= '1';
           end if;

           CfgCurrent.frame_type <= CfgNext.frame_type;
           CfgCurrent.binning_en <= CfgNext.binning_en;
           CfgCurrent.colStart   <= CfgNext.colStart;
           CfgCurrent.imageWidth <= CfgNext.imageWidth;
           CfgCurrent.image_size <= CfgNext.image_size;

        end if;
        -- when the correction data are valid store them also in the next item since the info is available before exposure

        if SENSOR_TEMP_VAL = '1' then
           CfgCurrent.sensorTemp <= SENSOR_TEMP; -- 
        end if;

        if TIME_STAMP_VAL = '1' then
           CfgCurrent.time <= TIME_STAMP;
        end if;

        AncDataVal <= '0';
        if ANC_INFO_READY = '1' then
           AncDataVal <= '1';
           if CfgCurrent.frame_type = C_PAN then 
              if ()
              PanAncId      <= PanAncId + 1;
           else
              HsAncId <= HsAncId + 1;
           end if;

        end if;
     end if;
  end if;

end process;

HS_ANC_ID <= std_logic_vector(HsAncId); HS_ANC_DATA <= CfgCurrent; HS_ANC_DATA_VAL <= AncDataVal;
PAN_ANC_ID <= std_logic_vector(PanAncId); PAN_ANC_DATA <= CfgCurrent; PAN_ANC_DATA_VAL <= AncDataVal;

-- END --

end rtl;

TypeError: Cannot read properties of undefined (reading 'match') at beautifyBrackets (c:\Users\kv.vscode\extensions\pretty-vhdl-main\out\src\VHDLFormatter\VHDLFormatter.js:1208:30)

kv-be commented 5 months ago

solved