There are cases of use of an identifier without declaring it previously. It is done in the file Identifier Renaming Visitor. Today we maintain a list of vars that have been used but not declared yet to declare later, since Verilog accepts this behavior, we must consider if it is worth forcing these declarations at the end of a module or changing it to increase acceptance.
rafasumi
commented
2 months ago
There are cases of use of an identifier without declaring it previously. It is done in the file Identifier Renaming Visitor. Today we maintain a list of vars that have been used but not declared yet to declare later, since Verilog accepts this behavior, we must consider if it is worth forcing these declarations at the end of a module or changing it to increase acceptance.