lac-dcc / chimera

A tool for synthesizing Verilog programs
GNU General Public License v3.0
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Investigate production of real types #4

Closed joaovam closed 2 months ago

joaovam commented 2 months ago

Some types are being marked as the type real while doing type inference when they should not be real, there is only one production that generates this constraint today, the node Tk_realtime.