lac-dcc / chimera

A tool for synthesizing Verilog programs
GNU General Public License v3.0
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variable is written to by both continuous and procedural assignments #47

Closed joaovam closed 1 month ago

joaovam commented 1 month ago
module module_1 (
    input wand id_0,
    input wor  id_1
);
  logic id_2 = 1;
  assign id_2 = id_1;

Map logic id_2 = 1 as a procedural assignment

Seed: 2861603525