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laforest / FPGADesignElements

A self-contained online book containing a library of FPGA design modules and related coding/design guides.
MIT License
387 stars 40 forks source link

Consider adding Verible and/or Surelog to verilinter? #13

Open mithro opened 3 years ago

mithro commented 3 years ago

You might want to consider adding Google's Verible and/or Surelog to your verilinter script. Verible provides precompiled binaries for most common Linux systems and is under <10mb it seems.

Verible can also be used to do code formatting if that is of interest.

Both Surelog and Verible should be able to parse anything that Icarus and Verilator can already parse, if you start using them and find anything which doesn't, please do log bugs on the associated repositories.

laforest commented 3 years ago

Can Verible and Surelog lint for only the synthesizable subset of Verilog-2001, rather than SystemVerilog? I use a subset of that subset when writing code to maximize portability and to reduce the number of bugs from Verilog corner-cases and varying support from CAD tools.