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laforest / FPGADesignElements

A self-contained online book containing a library of FPGA design modules and related coding/design guides.
MIT License
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fix bug #15

Closed pwang7 closed 2 years ago

pwang7 commented 2 years ago

The Adder_Subtractor_Binary_Multiprecision module has an input add_sub, So the Adder_Subtractor_Binary instance inside it should set its add_sub using the outer module input.

laforest commented 2 years ago

Unfortunately, it's not that simple. Look under the "Input Pipeline for B" section. Because of complications with carry bits, the B input is "manually" negated if add_sub is set to 1. Thus, the Adder_subtractor_Binary is always adding.

pwang7 commented 2 years ago

Unfortunately, it's not that simple. Look under the "Input Pipeline for B" section. Because of complications with carry bits, the B input is "manually" negated if add_sub is set to 1. Thus, the Adder_subtractor_Binary is always adding.

Sorry, my bad, will close this PR.

BTW, would you like add some testbench? If you like, I can add some.

laforest commented 2 years ago

No worries. I'm glad you are looking. :) I would rather leave testbenches out of the library. They go stale very very quickly. Please write any testbench you need, and if you find a bug, then the bugfix is great PR material. Thanks!