search

laforest / FPGADesignElements

A self-contained online book containing a library of FPGA design modules and related coding/design guides.
MIT License
401 stars 42 forks source link

Verilator complain about Carryin_binary.v #5

Closed rodrigomelo9 closed 4 years ago

rodrigomelo9 commented 4 years ago

Let me start saying that, after patch the 0 values/empty-strings of your files, it is the only remain Verilator complain :-) (there are still some iverilog complains, may be also related with other things to be changed).

%Warning-WIDTH: examples/CarryIn_Binary.v:31: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS's CONST '1'h0' generates 1 bits.

It can be solved changing carryin = 1'b0; by carryin = {WORD_WIDTH{1'b0}}; in the initial block. I don't know if you accept PR (let me know for future cases).

laforest commented 4 years ago

Good catch! That's exactly the right fix. I never saw it before because I only used it to calculate the final carry-in (for overflow calculations). Yes, I accept PRs. Just make sure to run ./v2h.py on the updated verilog file too.