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laforest / FPGADesignElements

A self-contained online book containing a library of FPGA design modules and related coding/design guides.
MIT License
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Fixed iVerilog error on the priority/round-robin arbiter #9

Closed rodrigomelo9 closed 4 years ago

rodrigomelo9 commented 4 years ago

An iverilog error because reg was used instead of wire in an output connected to an instantiated module.

laforest commented 4 years ago

Thanks. This is something the Verilator linter doesn't catch. I think it's technically legal, but I'm not sure how or when.