laforest / Octavo

Verilog FPGA Parts Library. Old Octavo soft-CPU project.
http://fpgacpu.ca/
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Convert wren/rden signals to req/ack form #20

Closed laforest closed 11 years ago

laforest commented 11 years ago

There are several ways to label the signals of a 4-phase handshake. I think they should just be "req/ack", regardless if they are used synchronously (as "ready" signals).

Naming:

This change should be doable with a careful search/replace. Though please do it on a separate branch.