Use case: too few multipliers on Cyclone devices (see #25), so it might be good to share a multiplier between two cores as an I/O module, where one core's even-numbered threads can write to the multiplier, and other other core's odd-numbered threads can. (Writing during the wrong thread just loses the data)
Generalized: a parameterizable mux and counter to connect N cores to 1 functional unit, where each core can access the FU once every 2nd, 3rd, 4th, etc...thread.
Use case: too few multipliers on Cyclone devices (see #25), so it might be good to share a multiplier between two cores as an I/O module, where one core's even-numbered threads can write to the multiplier, and other other core's odd-numbered threads can. (Writing during the wrong thread just loses the data)
Generalized: a parameterizable mux and counter to connect N cores to 1 functional unit, where each core can access the FU once every 2nd, 3rd, 4th, etc...thread.