laforest / Octavo

Verilog FPGA Parts Library. Old Octavo soft-CPU project.
http://fpgacpu.ca/
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Create cycle counters #41

Closed laforest closed 5 years ago

laforest commented 10 years ago

Extension on #40

Have the counter decrement every thread cycle instead of every branch test, to act as a thread cycle counter. Branch on same BTM entry as in #40 .

Decrement each clock tick to implement clock cycle counter.

Use some High mem bits to select behaviour.