It turns out that Verilog 'if' statements do not propagate X values.
if (a == b) begin
c <= d;
end
else begin
c <= e;
end
If b = X, then it's treated as a == 0, and c (tends to!) get e, not X.
However, c <= (a == b) ? d : e; will propagate X as expected.
On FPGAs, since we can state the initial register value at configuration, we don't see Xs, and with proper X handling where we consider all cases and generate X on default, we limit their propagation and generation.
However, moving forward, all conditionals should be converted to ternary statements or case blocks, leaving if statements solely for generate blocks. this will improve testing, especially if a future ASIC implementation happens.
Reference: "The Dangers of Living with an X" (ARM paper) http://www.arm.com/files/pdf/Verilog_X_Bugs.pdf
It turns out that Verilog 'if' statements do not propagate X values.
If
b = X, then it's treated asa == 0, andc(tends to!) gete, notX.However,
c <= (a == b) ? d : e;will propagateXas expected.On FPGAs, since we can state the initial register value at configuration, we don't see
Xs, and with properXhandling where we consider allcases and generateXondefault, we limit their propagation and generation.However, moving forward, all conditionals should be converted to ternary statements or case blocks, leaving
ifstatements solely forgenerateblocks. this will improve testing, especially if a future ASIC implementation happens.