Increase the number of branch condition flags

laforest / Octavo

Verilog FPGA Parts Library. Old Octavo soft-CPU project.

http://fpgacpu.ca/

Other

73 stars 14 forks source link

Closed laforest closed 5 years ago

laforest commented 9 years ago

Currently, the BTMs support 8 conditions, based of a 3-bit binary flag selector. Can we increase this to 16 without impacting Fmax? Related: #40