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laforest / Octavo

Verilog FPGA Parts Library. Old Octavo soft-CPU project.
http://fpgacpu.ca/
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Check AOM/BTM MLAB usage efficiency #58

Closed laforest closed 8 years ago

laforest commented 9 years ago

The AOM/BTM were implemented for design space exploration, so each branch and offset entry is described as a separate memory instance. It is unknown if Quartus correctly infers that these memories are all addressed in contiguous and non-overlapping ways, and so condenses them into fewer MLABs. Especially given that many of the AOM/BTM entries are mapped along a single memory word.

Also, Quartus may be using MLABs more finely (per ALM, rather than per LAB), making space optimizations in the source moot.

Solving #46 may also moot this issue, as it will remove the big muxes, and reduce all these simultaneously addressed memories into single ones addressed by the LSBs of the Address.

laforest commented 8 years ago

At least on Cyclone V, under Quartus Prime Lite 15.1, MLABs are not merged. Nor are they used in a sub-MLAB granularity. Each inferred MLAB memory uses a minimum of 10 ALMs (one whole MLAB). In hindsight this was too much to ask of the CAD tools. Will address in #62 .