laforest / Octavo

Verilog FPGA Parts Library. Old Octavo soft-CPU project.
http://fpgacpu.ca/
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Replace "===" with "==" where used for synthesis #63

Closed laforest closed 8 years ago

laforest commented 8 years ago

"===" does a direct comparison on 0,1,Z,X, which is not the intended behaviour for synthesis. (But this would be good for verification, where we may expect Z or X on some inputs) Instead, use "==" which returns X if an operand is X or Z, which matches synthesis behaviour.