Rather than map an I/O port to a single address, map it to a small range of N consecutive addresses.
Internally, there remains only one mux input for that I/O port, which minimizes that critical path, and we can decode the (translated) LSBs to obtain N separate enable signals.
This change should allow a higher usage rate of I/O ports, enabling N accelerators on a single port rather than N ports.
Rather than map an I/O port to a single address, map it to a small range of N consecutive addresses. Internally, there remains only one mux input for that I/O port, which minimizes that critical path, and we can decode the (translated) LSBs to obtain N separate enable signals.
This change should allow a higher usage rate of I/O ports, enabling N accelerators on a single port rather than N ports.