Closed TopGun-DICD closed 6 years ago
module inv(in, out); reg out; input in; output out;
always @in begin if(in == 0) begin out = 1; end if(in == 1) begin out = 0; end end endmodule
Done
module inv(in, out); reg out; input in; output out;
always @in begin if(in == 0) begin out = 1; end if(in == 1) begin out = 0; end end endmodule