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(< +nan.0 0.0) returns true on ARM #800

Closed WillClinger closed 7 years ago

WillClinger commented 7 years ago 
Larceny v0.99 "Goldie" (May 25 2016 13:51:21, precise:Linux:split)
larceny.heap, built on Wed May 25 13:57:00 UTC 2016

> (< +nan.0 0.0)
#t
> (< 0.0 +nan.0)
#t
> (> +nan.0 0.0)
#f
> (> 0.0 +nan.0)
#f
> (define x +nan.0)
x
> (define y 0.0)
y
> (< x y)
#f
> (< y x)
#f

In the first two examples above, representation inference converts the calls to < into calls to <:flo:flo. Similarly for calls to fl<?, where the call to < always turns into a call to <:flo:flo. We are evidently generating incorrect code for that flonum comparison.

% cat temp.sch
(define x +nan.0)
(define y 1.0)

(define (g0 x y)
  (fl=? x y))

(define (g1 x y)
  (fl<? x y))

(define (g2 x y)
  (fl>? x y))

Compiling with the new register assignments:

> (compile-file "/tmp/temp.sch")

> (load "/tmp/temp.fasl")

> (g0 x y)
#f

> (g1 x y)
#t

> (g2 x y)
#f

> (disassemble g0)
0000    e3 5a 00 08     cmpi     r10, #x8
0004    13 00 b0 08     movwi.ne r11, #x8
0008    12 89 ff 92     addi.ne  pc, r9, #x248
000c    e2 01 e0 07     andi     lr, r1, #x7
0010    e3 5e 00 05     cmpi     lr, #x5
0014    05 11 c0 05     ldri.eq  r12, [r1, -5]
0018    02 0c e0 ff     andi.eq  lr, r12, #xff
001c    1a 00 00 14     b.ne     #x74
0020    e3 5e 00 ca     cmpi     lr, #xca
0024    02 02 e0 07     andi.eq  lr, r2, #x7
0028    1a 00 00 11     b.ne     #x74
002c    e3 5e 00 05     cmpi     lr, #x5
0030    05 12 c0 05     ldri.eq  r12, [r2, -5]
0034    02 0c e0 ff     andi.eq  lr, r12, #xff
0038    1a 00 00 0a     b.ne     #x68
003c    e3 5e 00 ca     cmpi     lr, #xca
0040    02 81 e0 03     addi.eq  lr, r1, #x3
0044    0d 9e 0b 00     vldri.eq d0, [lr, 0]
0048    02 82 e0 03     addi.eq  lr, r2, #x3
004c    0d 9e 1b 00     vldri.eq d1, [lr, 0]
0050    0e b4 0b 41     vcmp.eq  d0, d1
0054    1a 00 00 03     b.ne     #x68
0058    ee f1 fa 10     vmrs     APSR_nzcv
005c    e3 00 a0 02     movwi    r10, #x2
0060    02 8a a0 04     addi.eq  r10, r10, #x4
0064    e5 98 f0 00     ldri     pc, [r8, 0]
0068    e1 a0 a0 02     mov      r10, r2
006c    e3 00 c0 b7     movwi    r12, #xb7
0070    e2 89 ff 80     addi     pc, r9, #x200
0074    e1 a0 a0 01     mov      r10, r1
0078    e3 00 c0 b7     movwi    r12, #xb7
007c    e2 89 ff 80     addi     pc, r9, #x200

> (disassemble g1)
0000    e3 5a 00 08     cmpi     r10, #x8
0004    13 00 b0 08     movwi.ne r11, #x8
0008    12 89 ff 92     addi.ne  pc, r9, #x248
000c    e2 01 e0 07     andi     lr, r1, #x7
0010    e3 5e 00 05     cmpi     lr, #x5
0014    05 11 c0 05     ldri.eq  r12, [r1, -5]
0018    02 0c e0 ff     andi.eq  lr, r12, #xff
001c    1a 00 00 11     b.ne     #x68
0020    e3 5e 00 ca     cmpi     lr, #xca
0024    02 02 e0 07     andi.eq  lr, r2, #x7
0028    1a 00 00 0e     b.ne     #x68
002c    e3 5e 00 05     cmpi     lr, #x5
0030    05 12 c0 05     ldri.eq  r12, [r2, -5]
0034    02 0c e0 ff     andi.eq  lr, r12, #xff
0038    1a 00 00 0d     b.ne     #x74
003c    e3 5e 00 ca     cmpi     lr, #xca
0040    02 81 e0 03     addi.eq  lr, r1, #x3
0044    0d 9e 0b 00     vldri.eq d0, [lr, 0]
0048    02 82 e0 03     addi.eq  lr, r2, #x3
004c    0d 9e 1b 00     vldri.eq d1, [lr, 0]
0050    0e b4 0b 41     vcmp.eq  d0, d1
0054    1a 00 00 06     b.ne     #x74
0058    ee f1 fa 10     vmrs     APSR_nzcv
005c    e3 00 a0 02     movwi    r10, #x2
0060    b2 8a a0 04     addi.lt  r10, r10, #x4
0064    e5 98 f0 00     ldri     pc, [r8, 0]
0068    e1 a0 a0 01     mov      r10, r1
006c    e3 00 c0 b8     movwi    r12, #xb8
0070    e2 89 ff 80     addi     pc, r9, #x200
0074    e1 a0 a0 02     mov      r10, r2
0078    e3 00 c0 b8     movwi    r12, #xb8
007c    e2 89 ff 80     addi     pc, r9, #x200

> (disassemble g2)
0000    e3 5a 00 08     cmpi     r10, #x8
0004    13 00 b0 08     movwi.ne r11, #x8
0008    12 89 ff 92     addi.ne  pc, r9, #x248
000c    e2 01 e0 07     andi     lr, r1, #x7
0010    e3 5e 00 05     cmpi     lr, #x5
0014    05 11 c0 05     ldri.eq  r12, [r1, -5]
0018    02 0c e0 ff     andi.eq  lr, r12, #xff
001c    1a 00 00 14     b.ne     #x74
0020    e3 5e 00 ca     cmpi     lr, #xca
0024    02 02 e0 07     andi.eq  lr, r2, #x7
0028    1a 00 00 11     b.ne     #x74
002c    e3 5e 00 05     cmpi     lr, #x5
0030    05 12 c0 05     ldri.eq  r12, [r2, -5]
0034    02 0c e0 ff     andi.eq  lr, r12, #xff
0038    1a 00 00 0a     b.ne     #x68
003c    e3 5e 00 ca     cmpi     lr, #xca
0040    02 81 e0 03     addi.eq  lr, r1, #x3
0044    0d 9e 0b 00     vldri.eq d0, [lr, 0]
0048    02 82 e0 03     addi.eq  lr, r2, #x3
004c    0d 9e 1b 00     vldri.eq d1, [lr, 0]
0050    0e b4 0b 41     vcmp.eq  d0, d1
0054    1a 00 00 03     b.ne     #x68
0058    ee f1 fa 10     vmrs     APSR_nzcv
005c    e3 00 a0 02     movwi    r10, #x2
0060    c2 8a a0 04     addi.gt  r10, r10, #x4
0064    e5 98 f0 00     ldri     pc, [r8, 0]
0068    e1 a0 a0 02     mov      r10, r2
006c    e3 00 c0 ba     movwi    r12, #xba
0070    e2 89 ff 80     addi     pc, r9, #x200
0074    e1 a0 a0 01     mov      r10, r1
0078    e3 00 c0 ba     movwi    r12, #xba
007c    e2 89 ff 80     addi     pc, r9, #x200

I suspect we are misinterpreting the condition codes transferred by the vmrs APSR_nzcv instruction.

WillClinger commented 7 years ago

Fixed by changeset 0407ef7cf6ef74a75e120cc09990bc8644bda2a1