The network config files (under larpix/configs/controller/) used to describe the hydra network use three fields to specify the links between mosi/miso channels:
The way these fields are translated to links between chips is non-trivial to understand and doesn't lend itself to a easily interpretable format. This should be reworked.
The index of each array is used to index the neighboring chips to the "active" chip, i.e. {0=up, 1=left, 2=down, 3=right}. The miso_uart_map specifies which miso uart is used to send data to the neighboring chip, i.e. {up=miso3, left=miso0, down=miso1, right=miso2}. The mosi_uart_map specifies the mosi uart that is used to receive data from the neighboring chip, i.e. {up=mosi0, left=mosi1, down=mosi2, right=mosi3}. Finally, usds_link_map is used to specify the position of the "active" chip relative to the neighboring chip, i.e. {up=neighbor down, left=neighbor right, down=neighbor up, right=neighbor left}. Putting these together (remembering that the index of the array corresponds to a particular direction from the "active" chip), we get a config:
From this, it becomes easy to generate the uart channels for a downstream network that is complementary to the upstream network. The upstream miso uart for the active chip is simply miso_uart_map[chip_index] and the downstream miso uart for the neighbor chip then miso_uart_map[usds_link_map[chip_index]] (with the miso_uart_map specified by the neighboring chip's configuration).
You can then specify a complicated geometry relatively easily. For example, two chips connected via the "up" of chip A and the "left" of chip B could be specified by modifying the usds_link_map for the two chips:
Globally:
This seems simpler, but I have yet to work through a test case that also needs to modify the miso/mosi uart map to make sure this is still a reasonable format.
The network config files (under larpix/configs/controller/) used to describe the hydra network use three fields to specify the links between mosi/miso channels:
The way these fields are translated to links between chips is non-trivial to understand and doesn't lend itself to a easily interpretable format. This should be reworked.
I propose to use:
The index of each array is used to index the neighboring chips to the "active" chip, i.e.
{0=up, 1=left, 2=down, 3=right}. Themiso_uart_mapspecifies which miso uart is used to send data to the neighboring chip, i.e.{up=miso3, left=miso0, down=miso1, right=miso2}. Themosi_uart_mapspecifies the mosi uart that is used to receive data from the neighboring chip, i.e.{up=mosi0, left=mosi1, down=mosi2, right=mosi3}. Finally,usds_link_mapis used to specify the position of the "active" chip relative to the neighboring chip, i.e.{up=neighbor down, left=neighbor right, down=neighbor up, right=neighbor left}. Putting these together (remembering that the index of the array corresponds to a particular direction from the "active" chip), we get a config:From this, it becomes easy to generate the uart channels for a downstream network that is complementary to the upstream network. The upstream miso uart for the active chip is simply
miso_uart_map[chip_index]and the downstream miso uart for the neighbor chip thenmiso_uart_map[usds_link_map[chip_index]](with themiso_uart_mapspecified by the neighboring chip's configuration).You can then specify a complicated geometry relatively easily. For example, two chips connected via the "up" of chip A and the "left" of chip B could be specified by modifying the
usds_link_mapfor the two chips: Globally:Chip A:
Chip B:
This seems simpler, but I have yet to work through a test case that also needs to modify the miso/mosi uart map to make sure this is still a reasonable format.