Sub-project 3: Support for Intel IMCI

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• [x] Get to know architecture
• [x] Study programming interface
• [x] Coding
• [ ] Testing

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• Reference
  • Overview: Reference for Intrinsics Supporting Intel® Initial Many Core Instructions (Intel® IMCI)
  • Intel Xeon Phi Code Modernization Roadshow » Intel Xeon Phi Code Modernization Roadshow
  • Intel Intrinsics Guide

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Intro

• Best Practices for Vectorization Getting ready for Intel® Advanced Vector Extensions 512 (Intel® AVX-512)

current generation of Intel Xeon Phi co-processors (codename "Knight's Corner", abbreviated KNC) supports 512-bit SIMD instruction set called "Intel® Initial Many Core Instructions" (abbreviated Intel® IMCI). Intel IMCI is not "compatible with" and is not equialent to SSE, AVX, AVX2 or AVX-512 ISA. However it's officially announced that next planned generations of Xeon Phi (codename "Knight's Landing", abbreviated KNL) will support AVX-512 ISA. Both Intel IMCI (supported by KNC) and AVX-512 (to be supported by KNL) are 512-bit SIMD instruction sets, supporting FMA and allowing to pack 8 double precision or 16 single precision floating-point numbers, or 16 32-bit integers (i.e. two times "more" than AVX or AVX2).

• Are there SIMD(SSE / AVX) instructions in the x86-compatible accelerators Intel Xeon Phi? - Stack Overflow