Closed idibidiart closed 6 years ago
We will create an RTL (register transfer level) design using Verilog, similarly to what's described here.
We will not be coding in RTL (register transfer language) but the synthesis tools we use might use that as an intermediate step.
Oh cool!
For those from coming to this from CS as opposed to EE, it probably should be clear what RTL in your all-too-exciting roadmap stands for...
I've not worked with hardware since the late 80s but I'm taking a stab here
"In computer science, register transfer language (RTL) is a kind of intermediate representation (IR) that is very close to assembly language, such as that which is used in a compiler. It is used to describe data flow at the register-transfer level of an architecture."