longtable with float ends up rendering past end of page

[timsifive]

Brief outline of the bug

When a float ends up on the same page as a longtable something goes wrong and text ends up being rendered way too low (or even off) the page. In this example, on the bottom of page 4 you can see that text is rendered in the border area that should be left white. In my actual document the problem is that text ends up rendered off the page, but it requires packages that latexbug doesn't like.

This bug with fix is described in detail at https://www.latex-project.org/cgi-bin/ltxbugs2html.new?pr=tools/3512

Minimal example showing the bug

\RequirePackage{latexbug}    % <- first line

\newif\ifrelease
\releasetrue
\documentclass[twoside,11pt,openany]{book}
\setcounter{tocdepth}{4}
\setcounter{secnumdepth}{4}

\usepackage{graphicx}
\usepackage{array}
\usepackage{longtable}

\newenvironment{steps}[1]
  {
     \vspace{1ex}
     \noindent #1
     \begin{enumerate}
  }
  {
     \end{enumerate}
     \vspace{1ex}
 }

\setlength{\topmargin}{-0.5in}
\setlength{\textheight}{9in}
\setlength{\oddsidemargin}{0in}
\setlength{\evensidemargin}{0in}
\setlength{\textwidth}{6.5in}

\newcommand{\note}[1]{{\bf [ NOTE: #1 ]}}
\newcommand{\fixme}[1]{{\bf [ FIXME: #1 ]}}
\newcommand{\todo}[1]{\marginpar{\footnotesize #1}}

\newcommand{\wunits}[2]{\mbox{#1\,#2}}
\newcommand{\um}{\mbox{$\mu$m}}
\newcommand{\xum}[1]{\wunits{#1}{\um}}
\newcommand{\by}[2]{\mbox{#1$\times$#2}}
\newcommand{\byby}[3]{\mbox{#1$\times$#2$\times$#3}}

\newlength\savedwidth
\newcommand\whline[1]{%
  \noalign{%
    \global\savedwidth\arrayrulewidth\global\arrayrulewidth 1.5pt%
  }%
  \cline{#1}%
  \noalign{\vskip\arrayrulewidth}%
  \noalign{\global\arrayrulewidth\savedwidth}%
}

\newenvironment{tightlist}
{\begin{itemize}
 \setlength{\parsep}{0pt}
 \setlength{\itemsep}{-2pt}}
{\end{itemize}}

\newenvironment{titledtightlist}[1]
{\noindent
 ~~\textbf{#1}
 \begin{itemize}
 \setlength{\parsep}{0pt}
 \setlength{\itemsep}{-2pt}}
{\end{itemize}}

\newenvironment{commentary}
{ \vspace{-0.2in}
  \begin{quotation}
  \noindent
  \small \em
  \rule{\linewidth}{1pt}\\
}
{ 
  \end{quotation}
  \vspace{-0.2in}
}

\pagestyle{myheadings}
\setlength{\parindent}{0in}
\setlength{\parskip}{10pt}
\sloppy

\newcolumntype{I}{>{\centering\arraybackslash}p{0.18in}}
\newcolumntype{W}{>{\centering\arraybackslash}p{0.36in}}
\newcolumntype{F}{>{\centering\arraybackslash}p{0.54in}}
\newcolumntype{Y}{>{\centering\arraybackslash}p{0.72in}}
\newcolumntype{R}{>{\centering\arraybackslash}p{0.9in}}
\newcolumntype{S}{>{\centering\arraybackslash}p{1.08in}}
\newcolumntype{O}{>{\centering\arraybackslash}p{1.26in}}
\newcolumntype{E}{>{\centering\arraybackslash}p{1.44in}}
\newcolumntype{T}{>{\centering\arraybackslash}p{1.8in}}
\newcolumntype{M}{>{\centering\arraybackslash}p{2.2in}}
\newcolumntype{K}{>{\centering\arraybackslash}p{2.88in}}
\newcolumntype{U}{>{\centering\arraybackslash}p{3.6in}}
\newcolumntype{L}{>{\centering\arraybackslash}p{3.6in}}
\newcolumntype{J}{>{\centering\arraybackslash}p{4.5in}}

\newcommand{\instbit}[1]{\mbox{\scriptsize #1}}
\newcommand{\instbitrange}[2]{~\instbit{#1} \hfill \instbit{#2}~}
\newcommand{\reglabel}[1]{\hfill {\tt #1}\hfill\ }

\newcommand{\wiri}{\textbf{WIRI}}
\newcommand{\wpri}{\textbf{WPRI}}
\newcommand{\wlrl}{\textbf{WLRL}}
\newcommand{\warl}{\textbf{WARL}}

\usepackage{makeidx}
\makeindex

\usepackage{xspace}
\newcommand{\defregname}[2]{\providecommand{#1}{{\tt #2}\xspace}}
\newcommand{\deffieldname}[2]{\providecommand{#1}{{$|#2|$}\xspace}}
\deffieldname{\Fmprv}{MPRV}
\deffieldname{\Fmie}{MIE}
\deffieldname{\Fmxl}{MXL}
\defregname{\Rmisa}{misa}
\defregname{\Rmstatus}{mstatus}
\defregname{\Rmcause}{mcause}
\defregname{\Rmie}{mie}

\deffieldname{\Fasid}{ASID}
\defregname{\Rsatp}{satp}

\defregname{\Azero}{a0}
\defregname{\Aone}{a1}

\defregname{\Rzero}{zero}
\defregname{\Szero}{s0}
\defregname{\Sone}{s1}

\defregname{\Tzero}{t0}

\defregname{\Xzero}{x0}
\defregname{\Xone}{x1}
\defregname{\Xeight}{x8}
\defregname{\Xnine}{x9}
\defregname{\Xten}{x10}
\defregname{\Xeleven}{x11}
\defregname{\Xthirtyone}{x31}
\defregname{\Fone}{f1}
\defregname{\Rpc}{pc}
\defregname{\Rmhartid}{mhartid}
\defregname{\Rmepc}{mepc}
\defregname{\Rdataone}{data1}

\deffieldname{\Faction}{action}

    \gdef\GITHash{dd94ea06656c4f4c20a11dcda9509cec7ddade27}    \gdef\GITAbrHash{dd94ea0}    \gdef\GITAuthorDate{Tue Feb 19 08:48:44 2019 -0800}    \gdef\GITAuthorName{Tim Newsome}

\newcommand{\versionnum}{0.13.1\ifrelease\else-DRAFT\fi}

\begin{document}

\title{RISC-V External Debug Support\\
Version \versionnum\\
\GITHash
}
\author{Editors: \\
Tim Newsome \textless tim@sifive.com\textgreater, SiFive, Inc. \\
Megan Wachs \textless megan@sifive.com\textgreater, SiFive, Inc.}
\date{\GITAuthorDate}

\markboth{RISC-V External Debug Support Version \versionnum}
{RISC-V External Debug Support Version \versionnum}
\thispagestyle{empty}

\frontmatter

\ifrelease
\else
    \chapter{Preface}

    {\bf Warning! This draft specification will change before being accepted as
    standard, so implementations made to this draft specification will likely not
    conform to the future standard.}
\fi

\mainmatter

\newpage

\chapter{Debug Module (DM)} \label{dm}

\begin{steps}{The Debug Module implements a translation interface between abstract debug
    operations and their specific implementation. It might support the following
    operations:}
\item Give the debugger necessary information about the implementation. (Required)
\end{steps}

\begin{steps}{In order to be compliant with this specification an
    implementation must:}
\item
    \begin{steps}{Do at least one of:}
        \item Implement the Program Buffer.
        \item Implement abstract access to all registers that are visible to
            software running on the hart including all the registers that are
            present on the hart and listed in Table~\ref{tab:regno}.
        \item Implement abstract access to at least all GPRs, Rdcsr, and
            Rdpc, and advertise the implementation as conforming to the
            ``Minimal RISC-V Debug Specification \versionnum'', instead of the
            ``RISC-V Debug Specification \versionnum''.
    \end{steps}
\end{steps}

A single DM can debug up to $2^{20}$ harts.

\section{Abstract Commands} \label{abstractcommands}

The DM supports a set of abstract commands, most of which
are optional. Depending on the implementation, the debugger may
be able to perform
some abstract commands even when the selected hart is not halted.
Debuggers can only determine which abstract commands
are supported by a given hart in a given state by attempting them
and then looking at Fcmderr in Rabstractcs to see if they were successful.
Commands may be supported with some options set, but not with other options
set. If a command has unsupported options set, the DM must set Fcmderr to 2
(not supported).

\begin{commentary}
    Example: Every system must support the Access Register command, but may not
    support accessing CSRs. If the debugger requests to read a CSR in that
    case, the command will return ``not supported.''
\end{commentary}

Debuggers execute abstract commands by writing them to Rcommand.  They
can determine whether an abstract command is complete by reading Fbusy in
Rabstractcs. After completion, Fcmderr indicates whether the command was
successful or not. Commands may fail because a hart is not halted, not running,
unavailable, or because they encounter an error during execution.

If the command takes arguments, the debugger
must write them to the {\tt data} registers before writing to Rcommand. If a
command returns results, the Debug Module must ensure they are placed
in the {\tt data} registers before Fbusy is cleared.
Which {\tt data} registers are used for the arguments is
described in Table~\ref{tab:datareg}.  In all cases the least-significant word
is placed in the lowest-numbered {\tt data} register. The argument width
depends on the command being executed, and is DXLEN where not explicitly
specified.

\begin{table}[htp]
    \centering
    \caption{Use of Data Registers}
    \label{tab:datareg}
    \begin{tabular}{|r|l|l|l|}
        \hline
        Argument Width & arg0/return value & arg1 & arg2 \\
        \hline
        32 & Rdatazero & {\tt data1} & {\tt data2} \\
        \hline
        64 & Rdatazero, {\tt data1} & {\tt data2}, {\tt data3} & {\tt data4}, {\tt data5} \\
        \hline
        128 & Rdatazero--{\tt data3} & {\tt data4}--{\tt data7} & {\tt data8}--{\tt data11} \\
        \hline
    \end{tabular}
\end{table}

\begin{commentary}
    The Abstract Command interface is designed to allow a debugger to write
    commands as fast as possible, and then later check whether they completed
    without error.  In the common case the debugger will be much slower than
    the target and commands succeed, which allows for maximum throughput. If
    there is a failure, the interface ensures that no commands execute after
    the failing one.  To discover which command failed, the debugger has to
    look at the state of the DM (e.g.\ contents of Rdatazero) or hart (e.g.\ 
    contents of a register modified by a Program Buffer program) to determine
    which one failed.
\end{commentary}

Before starting an abstract command, a debugger must ensure that Fhaltreq,
Fresumereq, and Fackhavereset are all 0.

While an abstract command is executing (Fbusy in Rabstractcs is high), a
debugger must not change Fhartsel, and must not write 1 to Fhaltreq,
Fresumereq, Fackhavereset, Fsetresethaltreq, or Fclrresethaltreq.

If an abstract command does not complete in the expected time and appears to be
hung, the following procedure can be attempted to abort the command: First the
debugger resets the hart (using Fhartreset or Fndmreset), and then it resets
the Debug Module (using Fdmactive).

If an abstract command is started while the selected hart is unavailable or if
a hart becomes unavailable while executing an abstract command, then the
Debug Module may terminate the abstract command, setting Fbusy low, and
Fcmderr to 4 (halt/resume). Alternatively, the command could just appear to be
hung (Fbusy never goes low).

\subsection{Abstract Command Listing}

This section describes each of the different abstract commands
and how their fields should be interpreted when
they are written to Rcommand.

Each abstract command is a 32-bit value. The top 8 bits contain Fcmdtype which
determines the kind of command. Table~\ref{tab:cmdtype} lists all commands.

\begin{table}[htp]
    \centering
    \caption{Meaning of Fcmdtype}
    \label{tab:cmdtype}
    \begin{tabular}{|r|l|l|l|}
        \hline
        Fcmdtype & Command & Page \\
        \hline
        0 & Access Register Command & \pageref{access register} \\
        \hline
        1 & Quick Access & \pageref{quick access} \\
        \hline
        2 & Access Memory Command & \pageref{access memory} \\
        \hline
    \end{tabular}
\end{table}

\subsubsection{Access Register}
\index{Access Register}
\label{access register}
\begin{steps}{This command gives the debugger access to CPU registers
        and allows it to execute the Program Buffer.
        It performs the following sequence of operations:}
        \item If Fwrite is clear and Ftransfer is set, then copy data from
            the register specified by Fregno into the {\tt arg0} region of
            {\tt data}, and perform any side effects that occur when this
            register is read from M-mode.
        \item If Fwrite is set and Ftransfer is set, then copy data from the
            {\tt arg0} region of {\tt data} into the register specified by
            Fregno, and perform any side effects that occur when this register
            is written from M-mode.
        \item If Faarpostincrement is set, increment Fregno.
        \item Execute the Program Buffer, if Fpostexec is set.
        \end{steps}

        If any of these operations fail, Fcmderr is set and none of the
        remaining steps are executed. An implementation may detect an upcoming
        failure early, and fail the overall command before it reaches the step
        that would cause failure. If the failure is that the requested register
        does not exist in the hart, Fcmderr must be set to 3 (exception).

        Debug Modules must implement this command
        and must support read and write access to all GPRs when the selected hart is halted.
        Debug Modules may optionally support accessing other registers,
        or accessing registers when the hart is running.
        Each individual register (aside from GPRs) may be supported differently
        across read, write, and halt status.

        \begin{table}[htp]
            \centering
            \caption{Abstract Register Numbers}
            \label{tab:regno}
            \begin{tabular}{|r|l|}
                \hline
                0x0000 -- 0x0fff & CSRs. The ``PC'' can be accessed here through Rdpc.
                \\
                \hline
                0x1000 -- 0x101f & GPRs \\
                \hline
                0x1020 -- 0x103f & Floating point registers \\
                \hline
                0xc000 -- 0xffff & Reserved for non-standard extensions and internal
                use. \\
                \hline
            \end{tabular}
        \end{table}

        \begin{commentary}
            The encoding of Faarsize was chosen to match Fsbaccess in Rsbcs.
        \end{commentary}

        This command modifies {\tt arg0} only when a register is read. The
        other {\tt data} registers are not changed.

\begin{center}
\begin{tabular}{p{4.0 ex}p{4.0 ex}p{2.4 ex}p{2.4 ex}p{3.5 ex}p{3.5 ex}p{8.0 ex}p{8.0 ex}}
{\scriptsize 31} &
\multicolumn{1}{r}{\scriptsize 24}
&
\multicolumn{2}{c}{\scriptsize 23}
&
{\scriptsize 22} &
\multicolumn{1}{r}{\scriptsize 20}
&
\multicolumn{2}{c}{\scriptsize 19}
\\
         \hline
\multicolumn{2}{|c|}{$|cmdtype|$}
&
\multicolumn{2}{c|}{$|0|$}
&
\multicolumn{2}{c|}{$|aarsize|$}
&
\multicolumn{2}{c|}{$|aarpostincrement|$}
\\
         \hline
\multicolumn{2}{c}{\scriptsize 8} & \multicolumn{2}{c}{\scriptsize 1} & \multicolumn{2}{c}{\scriptsize 3} & \multicolumn{2}{c}{\scriptsize 1}
\\
   \end{tabular}
\begin{tabular}{p{4.0 ex}p{4.0 ex}p{4.0 ex}p{4.0 ex}p{2.5 ex}p{2.5 ex}p{10.7 ex}p{5.3 ex}}
\multicolumn{2}{c}{\scriptsize 18}
&
\multicolumn{2}{c}{\scriptsize 17}
&
\multicolumn{2}{c}{\scriptsize 16}
&
{\scriptsize 15} &
\multicolumn{1}{r}{\scriptsize 0}
\\
         \hline
\multicolumn{2}{|c|}{$|postexec|$}
&
\multicolumn{2}{c|}{$|transfer|$}
&
\multicolumn{2}{c|}{$|write|$}
&
\multicolumn{2}{c|}{$|regno|$}
\\
         \hline
\multicolumn{2}{c}{\scriptsize 1} & \multicolumn{2}{c}{\scriptsize 1} & \multicolumn{2}{c}{\scriptsize 1} & \multicolumn{2}{c}{\scriptsize 16}
\\
   \end{tabular}
\end{center}
\begin{center}
   \begin{longtable}{|l|p{0.5\textwidth}|}
   \hline
   Field & Description\\
   \hline
   \endhead
   \multicolumn{2}{r}{\textit{Continued on next page}} \\
   \endfoot
   \endlastfoot
\label{cmdtype}
\index{cmdtype}
   |cmdtype| & This is 0 to indicate Access Register Command.\\
   \hline
\label{aarsize}
\index{aarsize}
   |aarsize| & 2: Access the lowest 32 bits of the register.

            3: Access the lowest 64 bits of the register.

            4: Access the lowest 128 bits of the register.

            This field controls the Argument Width as referenced in
            Table~\ref{tab:datareg}.\\
   \hline
\label{aarpostincrement}
\index{aarpostincrement}
   |aarpostincrement| & 0: No effect. This variant must be supported.

            1: After a successful register access, Fregno is incremented
            (wrapping around to 0). Supporting this variant is optional.\\
   \hline
\label{postexec}
\index{postexec}
   |postexec| & 0: No effect. This variant must be supported, and is the only
            supported one if Fprogbufsize is 0.

            1: Execute the program in the Program Buffer exactly once after
            performing the transfer, if any. Supporting this variant is
            optional.\\
   \hline
\label{transfer}
\index{transfer}
   |transfer| & 0: Don't do the operation specified by Fwrite.

            1: Do the operation specified by Fwrite.

            This bit can be used to just execute the Program Buffer without
            having to worry about placing valid values into Faarsize or Fregno.\\
   \hline
\label{write}
\index{write}
   |write| & When Ftransfer is set:
            0: Copy data from the specified register into {\tt arg0} portion
               of {\tt data}.

            1: Copy data from {\tt arg0} portion of {\tt data} into the
               specified register.\\
   \hline
\label{regno}
\index{regno}
   |regno| & Number of the register to access, as described in
          Table~\ref{tab:regno}.
          Rdpc may be used as an alias for PC if this command is
          supported on a non-halted hart.\\
   \hline
   \end{longtable}
\end{center}

\subsubsection{Quick Access}
\index{Quick Access}
\label{quick access}
\begin{steps}{Perform the following sequence of operations:}
        \item If the hart is halted, the command  sets Fcmderr to ``halt/resume'' and does not continue.
        \item Halt the hart. If the hart halts for some other reason (e.g. breakpoint), the command
            sets Fcmderr to ``halt/resume'' and does not continue.
        \item Execute the Program Buffer. If an exception occurs, Fcmderr is set to ``exception''
            and the program buffer execution ends, but the quick access command continues.
        \item Resume the hart.
        \end{steps}

        Implementing this command is optional.

        This command does not touch the {\tt data} registers.

\begin{center}
\begin{tabular}{p{4.0 ex}p{4.0 ex}p{16.0 ex}p{8.0 ex}}
{\scriptsize 31} &
\multicolumn{1}{r}{\scriptsize 24}
&
{\scriptsize 23} &
\multicolumn{1}{r}{\scriptsize 0}
\\
         \hline
\multicolumn{2}{|c|}{$|cmdtype|$}
&
\multicolumn{2}{c|}{$|0|$}
\\
         \hline
\multicolumn{2}{c}{\scriptsize 8} & \multicolumn{2}{c}{\scriptsize 24}
\\
   \end{tabular}
\end{center}
   %{{Continued on next page}} \\ \hline}
\begin{center}
   \begin{longtable}{|l|p{0.5\textwidth}|}
   \hline
   Field & Description\\
   \hline
   \endhead
   \multicolumn{2}{r}{\textit{Continued on next page}} \\
   \endfoot
   \endlastfoot
\label{cmdtype}
\index{cmdtype}
   |cmdtype| & This is 1 to indicate Quick Access command.\\
   \hline
   \end{longtable}
\end{center}

\end{document}

Log file (required) and possibly PDF file

riscv-debug-latex-issue.log riscv-debug-latex-issue.pdf

[stale[bot]]

This issue has been automatically marked as stale because it has not had recent activity. It will be closed if no further activity occurs. Thank you for your contributions.

[davidcarlisle]

This is probably ttp://www.latex-project.org/cgi-bin/ltxbugs2html?pr=tools/3512 I do hope to address this along with other issues: http://htmlpreview.github.io/?https://raw.githubusercontent.com/davidcarlisle/dpctex/master/longtable/ltbugs.html

[stale[bot]]

This issue has been automatically marked as stale because it has not had recent activity.

[stale[bot]]

This issue has been automatically marked as stale because it has not had recent activity.

[stale[bot]]

This issue has been automatically marked as stale because it has not had recent activity.

[u-fischer]

@cpmech the issue here has been fixed. When I compile the original MWE in a current texlive 2024 it no longer spills over the page border. Open a new issue with a complete example of your problem.