long771
commented
8 months ago 这是来自QQ邮箱的自动回复邮件。 您好，我是龙欣荣，很高兴收到您的邮件，我将尽快处理。
Open dimen100 opened 8 months ago
long771
commented
8 months ago 这是来自QQ邮箱的自动回复邮件。 您好，我是龙欣荣，很高兴收到您的邮件，我将尽快处理。
laurencebarker
commented
8 months ago You are running a script created by Xilinx software. The usual things that upset it are:
I’m guessing you have got past the first one…. You should have vivado 2023.1.
Do either of those help?
Laurence Barker G8NJJ
@.***
From: dimen100 @.> Sent: Tuesday, January 16, 2024 5:16 AM To: laurencebarker/Saturn @.> Cc: Subscribed @.***> Subject: [laurencebarker/Saturn] ERROR: [IP_Flow 19-3478] (Issue #7)
I have to following error when trying to create project -
WARNING: [IP_Flow 19-5661] Bus Interface 'ACLK' does not have any bus interfaces associated with it. WARNING: [IP_Flow 19-11770] Clock interface 'ACLK' has no FREQ_HZ parameter. INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis' of definition 'xilinx.com:interface:axis:1.0' (from Xilinx Repository). INFO: [IP_Flow 19-5107] Inferred bus interface 'aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). INFO: [IP_Flow 19-5107] Inferred bus interface 'aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). INFO: [IP_Flow 19-4728] Bus Interface 'aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. INFO: [IP_Flow 19-4728] Bus Interface 'aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 'm_axis'. INFO: [IP_Flow 19-4728] Bus Interface 'aclk': Added interface parameter 'ASSOCIATED_RESET' with value 'aresetn'. WARNING: [IP_Flow 19-11770] Clock interface 'aclk' has no FREQ_HZ parameter. INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis' of definition 'xilinx.com:interface:axis:1.0' (from Xilinx Repository). INFO: [IP_Flow 19-5107] Inferred bus interface 'aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). INFO: [IP_Flow 19-4728] Bus Interface 'aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 'm_axis'. WARNING: [IP_Flow 19-11770] Clock interface 'aclk' has no FREQ_HZ parameter. INFO: [IP_Flow 19-5107] Inferred bus interface 'ACLK' of definition 'xilinx.com:signal:clock:1.0' (from X_INTERFACE_INFO parameter from HDL file). INFO: [IP_Flow 19-5107] Inferred bus interface 'ACLK' of definition 'xilinx.com:signal:clock:1.0' (from 'X_INTERFACE_INFO' attribute). INFO: [IP_Flow 19-5107] Inferred bus interface 'resetn' of definition 'xilinx.com:signal:reset:1.0' (from X_INTERFACE_INFO parameter from HDL file). INFO: [IP_Flow 19-5107] Inferred bus interface 'resetn' of definition 'xilinx.com:signal:reset:1.0' (from 'X_INTERFACE_INFO' attribute). INFO: [IP_Flow 19-4728] Bus Interface 'ACLK': Added interface parameter 'ASSOCIATED_RESET' with value 'resetn'. INFO: [IP_Flow 19-4728] Bus Interface 'resetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. WARNING: [IP_Flow 19-5661] Bus Interface 'ACLK' does not have any bus interfaces associated with it. WARNING: [IP_Flow 19-11770] Clock interface 'ACLK' has no FREQ_HZ parameter. INFO: [IP_Flow 19-5107] Inferred bus interface 'ACLK' of definition 'xilinx.com:signal:clock:1.0' (from X_INTERFACE_INFO parameter from HDL file). INFO: [IP_Flow 19-5107] Inferred bus interface 'ACLK' of definition 'xilinx.com:signal:clock:1.0' (from 'X_INTERFACE_INFO' attribute). INFO: [IP_Flow 19-5107] Inferred bus interface 'resetn' of definition 'xilinx.com:signal:reset:1.0' (from X_INTERFACE_INFO parameter from HDL file). INFO: [IP_Flow 19-5107] Inferred bus interface 'resetn' of definition 'xilinx.com:signal:reset:1.0' (from 'X_INTERFACE_INFO' attribute). INFO: [IP_Flow 19-4728] Bus Interface 'ACLK': Added interface parameter 'ASSOCIATED_RESET' with value 'resetn'. INFO: [IP_Flow 19-4728] Bus Interface 'resetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. WARNING: [IP_Flow 19-5661] Bus Interface 'ACLK' does not have any bus interfaces associated with it. WARNING: [IP_Flow 19-11770] Clock interface 'ACLK' has no FREQ_HZ parameter. INFO: [IP_Flow 19-5107] Inferred bus interface 'input_0_axis' of definition 'xilinx.com:interface:axis:1.0' (from Xilinx Repository). INFO: [IP_Flow 19-5107] Inferred bus interface 'input_1_axis' of definition 'xilinx.com:interface:axis:1.0' (from Xilinx Repository). INFO: [IP_Flow 19-5107] Inferred bus interface 'output_axis' of definition 'xilinx.com:interface:axis:1.0' (from Xilinx Repository). INFO: [IP_Flow 19-5107] Inferred bus interface 'rstn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). INFO: [IP_Flow 19-4728] Bus Interface 'rstn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. INFO: [IP_Flow 19-4728] Bus Interface 'clk': Added interface parameter 'ASSOCIATED_BUSIF' with value 'input_0_axis'. INFO: [IP_Flow 19-4728] Bus Interface 'clk': Added interface parameter 'ASSOCIATED_RESET' with value 'rstn'. INFO: [IP_Flow 19-818] Not transferring value dependency attribute "(spirit:decode(id('MODELPARAM_VALUE.DATA_WIDTH')) > 8)" into user parameter "KEEP_ENABLE". INFO: [IP_Flow 19-818] Not transferring value dependency attribute "(spirit:decode(id('MODELPARAM_VALUE.DATA_WIDTH')) / 8)" into user parameter "KEEP_WIDTH". WARNING: [IP_Flow 19-533] HDL Parameter 'KEEP_ENABLE (Keep Enable)': Missing data type WARNING: [IP_Flow 19-11770] Clock interface 'clk' has no FREQ_HZ parameter. INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis' of definition 'xilinx.com:interface:axis:1.0' (from Xilinx Repository). INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis' of definition 'xilinx.com:interface:axis:1.0' (from Xilinx Repository). INFO: [IP_Flow 19-5107] Inferred bus interface 'aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). INFO: [IP_Flow 19-5107] Inferred bus interface 'aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). INFO: [IP_Flow 19-4728] Bus Interface 'aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. INFO: [IP_Flow 19-4728] Bus Interface 'aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 'm_axis'. INFO: [IP_Flow 19-4728] Bus Interface 'aclk': Added interface parameter 'ASSOCIATED_RESET' with value 'aresetn'. WARNING: [IP_Flow 19-11770] Clock interface 'aclk' has no FREQ_HZ parameter. INFO: [IP_Flow 19-1976] HDL Parser: Replacing 'InitialValue' by 1 for port or parameter 'LFSR' INFO: [IP_Flow 19-5107] Inferred bus interface 'ACLK' of definition 'xilinx.com:signal:clock:1.0' (from X_INTERFACE_INFO parameter from HDL file). INFO: [IP_Flow 19-5107] Inferred bus interface 'ACLK' of definition 'xilinx.com:signal:clock:1.0' (from 'X_INTERFACE_INFO' attribute). INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis' of definition 'xilinx.com:interface:axis:1.0' (from Xilinx Repository). INFO: [IP_Flow 19-5107] Inferred bus interface 'aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). INFO: [IP_Flow 19-4728] Bus Interface 'aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. INFO: [IP_Flow 19-4728] Bus Interface 'ACLK': Added interface parameter 'ASSOCIATED_BUSIF' with value 'm_axis'. INFO: [IP_Flow 19-4728] Bus Interface 'ACLK': Added interface parameter 'ASSOCIATED_RESET' with value 'aresetn'. WARNING: [IP_Flow 19-11770] Clock interface 'ACLK' has no FREQ_HZ parameter. ERROR: [IP_Flow 19-3478] Validation failed for parameter 'M00 TDATA Remap String(M00_TDATA_REMAP)' with value 'tdata[31:0]' for BD Cell 'axis_broadcaster_0'. Validation failed for parameter 'M00 TDATA Remap String(M00_TDATA_REMAP)' with value 'tdata[31:0]' for BD Cell 'axis_broadcaster_0'. Range specification exceeds input signal width (8): tdata[31:0],Error: element tdata[31:0] makes remap too large!
ERROR: [IP_Flow 19-3478] Validation failed for parameter 'M01 TDATA Remap String(M01_TDATA_REMAP)' with value 'tdata[31:0]' for BD Cell 'axis_broadcaster_0'. Validation failed for parameter 'M01 TDATA Remap String(M01_TDATA_REMAP)' with value 'tdata[31:0]' for BD Cell 'axis_broadcaster_0'. Range specification exceeds input signal width (8): tdata[31:0],Error: element tdata[31:0] makes remap too large!
INFO: [IP_Flow 19-3438] Customization errors found on 'axis_broadcaster_0'. Restoring to previous valid configuration. INFO: [Common 17-17] undo 'set_property' ERROR: [Common 17-39] 'set_property' failed due to earlier errors.
while executing
"rdi::add_properties -dict {CONFIG.M00_TDATA_REMAP {tdata[31:0]} CONFIG.M01_TDATA_REMAP {tdata[31:0]}} /axis_broadcaster_0" invoked from within "set_property -dict [list CONFIG.M00_TDATA_REMAP {tdata[31:0]} CONFIG.M01_TDATA_REMAP {tdata[31:0]} ] $axis_broadcaster_0" (procedure "cr_bd_DDC_Block" line 253) invoked from within "cr_bd_DDC_Block """ (file "create_saturn_project.tcl" line 1090) update_compile_order -fileset sources_1
Appreciate your help
— Reply to this email directly, view it on GitHub https://github.com/laurencebarker/Saturn/issues/7 , or unsubscribe https://github.com/notifications/unsubscribe-auth/AEXTXZ7S6H2O3GBDCZCZ64DYOYEJZAVCNFSM6AAAAABB4GLL2GVHI2DSMVQWIX3LMV43ASLTON2WKOZSGA4DGMBTGY3DOOA . You are receiving this because you are subscribed to this thread. https://github.com/notifications/beacon/AEXTXZ7JTEGMHT7CITUD6L3YOYEJZA5CNFSM6AAAAABB4GLL2GWGG33NNVSW45C7OR4XAZNFJFZXG5LFVJRW63LNMVXHIX3JMTHHYKE6AY.gif Message ID: @. @.> >
dimen100
commented
8 months ago These are the steps you mentioned - Install vivado 2023.1 - done Copy this repository to c:\xilinxdesigns\saturn - you mean cd c:/xilinxdesigns/Saturn ? Open vivado and find the TCL command line - done type: cd c:/xilinxdesigns/Saturn/FPGA - done type: source create_saturn_project.tcl -done
Then the script won't run. Complains there is already a folder named "saturn_project" (which is TRUE, there is already a folder named "saturn_project" inside c:/xilinxdesigns/Saturn/FPGA )
So I did this -
I am running some part from a different location and using Vivado 2023.1
This is where the script now - C:\xilinxdesigns\Saturn\FPGA.
There is already a folder named "saturn_project" (inside FPGA folder)with some files in it when i download it form git.
So the script won't run. Complains there is already a folder named "saturn_project"
So i had to delete the "saturn_project" folder.
Then the script will start running a bit more but complain that it cant find folder "saturn_project.srcs" which was inside the previously deleted folder "saturn_project".
So I had to copy "saturn_project.srcs" out of "saturn_project" initially before running script and place it in the C:\xilinxdesigns\Saturn\FPGA and changed the location of this folder (saturn_project.srcs) in the script.
Then the script will run this far and will show the error in my previous post.
Can you please check initially why there is already a folder named "saturn_project" inside the FPGA folder. That is the first error I have.
Like you mentioned before - A new xilinx project will be created in the subdirectory FPGA\saturn_project - This is not happening because there is already FPGA\saturn_project folder when download from the git source.
Thankyou
laurencebarker
commented
8 months ago Try ignoring the script altogether. Instead open Saturn_project.xpr in the Saturn_project folder then build by selecting “generate bitstream”
Saturn is trapped between an “old” and a “new” Xilinx approach to directory structure and storing files in git. We don’t use that script except as a backup now; the sources should be in git directly.
Laurence Barker G8NJJ
@.***
From: dimen100 @.> Sent: Wednesday, January 17, 2024 3:00 AM To: laurencebarker/Saturn @.> Cc: Laurence Barker @.>; Comment @.> Subject: Re: [laurencebarker/Saturn] ERROR: [IP_Flow 19-3478] (Issue #7)
I am running it from a different location and using Vivado 2023.1 This is where the script is now - C:\xilinxdesigns\Saturn\FPGA, There is already a folder named "saturn_project" with some files in it when i download it form git. So the script won't run. Complains there is already a folder named "saturn_project" So i had to delete the "saturn_project" folder. Then the script will start running but complain that it cant find folder "saturn_project.srcs" which was inside the previously deleted folder "saturn_project". So I had to copy "saturn_project.srcs" out of "saturn_project" initially before running script and place it in the C:\xilinxdesigns\Saturn\FPGA and changed the location of this folder (saturn_project.srcs) in the script. Then the script will run this far. Can you please check initially why there is already a folder named "saturn_project" inside the FPGA folder. That is the first error I have. Thankyou
— Reply to this email directly, view it on GitHub https://github.com/laurencebarker/Saturn/issues/7#issuecomment-1894859781 , or unsubscribe https://github.com/notifications/unsubscribe-auth/AEXTXZ4DSAFXUAFP5PP4A6DYO45DNAVCNFSM6AAAAABB4GLL2GVHI2DSMVQWIX3LMV43OSLTON2WKQ3PNVWWK3TUHMYTQOJUHA2TSNZYGE . You are receiving this because you commented. https://github.com/notifications/beacon/AEXTXZ4AOCSBSSZKYGE653DYO45DNA5CNFSM6AAAAABB4GLL2GWGG33NNVSW45C7OR4XAZNMJFZXG5LFINXW23LFNZ2KUY3PNVWWK3TUL5UWJTTQ6FCAK.gif Message ID: @. @.> >
I have to following error when trying to create project -
WARNING: [IP_Flow 19-5661] Bus Interface 'ACLK' does not have any bus interfaces associated with it. WARNING: [IP_Flow 19-11770] Clock interface 'ACLK' has no FREQ_HZ parameter. INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis' of definition 'xilinx.com:interface:axis:1.0' (from Xilinx Repository). INFO: [IP_Flow 19-5107] Inferred bus interface 'aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). INFO: [IP_Flow 19-5107] Inferred bus interface 'aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). INFO: [IP_Flow 19-4728] Bus Interface 'aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. INFO: [IP_Flow 19-4728] Bus Interface 'aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 'm_axis'. INFO: [IP_Flow 19-4728] Bus Interface 'aclk': Added interface parameter 'ASSOCIATED_RESET' with value 'aresetn'. WARNING: [IP_Flow 19-11770] Clock interface 'aclk' has no FREQ_HZ parameter. INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis' of definition 'xilinx.com:interface:axis:1.0' (from Xilinx Repository). INFO: [IP_Flow 19-5107] Inferred bus interface 'aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). INFO: [IP_Flow 19-4728] Bus Interface 'aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 'm_axis'. WARNING: [IP_Flow 19-11770] Clock interface 'aclk' has no FREQ_HZ parameter. INFO: [IP_Flow 19-5107] Inferred bus interface 'ACLK' of definition 'xilinx.com:signal:clock:1.0' (from X_INTERFACE_INFO parameter from HDL file). INFO: [IP_Flow 19-5107] Inferred bus interface 'ACLK' of definition 'xilinx.com:signal:clock:1.0' (from 'X_INTERFACE_INFO' attribute). INFO: [IP_Flow 19-5107] Inferred bus interface 'resetn' of definition 'xilinx.com:signal:reset:1.0' (from X_INTERFACE_INFO parameter from HDL file). INFO: [IP_Flow 19-5107] Inferred bus interface 'resetn' of definition 'xilinx.com:signal:reset:1.0' (from 'X_INTERFACE_INFO' attribute). INFO: [IP_Flow 19-4728] Bus Interface 'ACLK': Added interface parameter 'ASSOCIATED_RESET' with value 'resetn'. INFO: [IP_Flow 19-4728] Bus Interface 'resetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. WARNING: [IP_Flow 19-5661] Bus Interface 'ACLK' does not have any bus interfaces associated with it. WARNING: [IP_Flow 19-11770] Clock interface 'ACLK' has no FREQ_HZ parameter. INFO: [IP_Flow 19-5107] Inferred bus interface 'ACLK' of definition 'xilinx.com:signal:clock:1.0' (from X_INTERFACE_INFO parameter from HDL file). INFO: [IP_Flow 19-5107] Inferred bus interface 'ACLK' of definition 'xilinx.com:signal:clock:1.0' (from 'X_INTERFACE_INFO' attribute). INFO: [IP_Flow 19-5107] Inferred bus interface 'resetn' of definition 'xilinx.com:signal:reset:1.0' (from X_INTERFACE_INFO parameter from HDL file). INFO: [IP_Flow 19-5107] Inferred bus interface 'resetn' of definition 'xilinx.com:signal:reset:1.0' (from 'X_INTERFACE_INFO' attribute). INFO: [IP_Flow 19-4728] Bus Interface 'ACLK': Added interface parameter 'ASSOCIATED_RESET' with value 'resetn'. INFO: [IP_Flow 19-4728] Bus Interface 'resetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. WARNING: [IP_Flow 19-5661] Bus Interface 'ACLK' does not have any bus interfaces associated with it. WARNING: [IP_Flow 19-11770] Clock interface 'ACLK' has no FREQ_HZ parameter. INFO: [IP_Flow 19-5107] Inferred bus interface 'input_0_axis' of definition 'xilinx.com:interface:axis:1.0' (from Xilinx Repository). INFO: [IP_Flow 19-5107] Inferred bus interface 'input_1_axis' of definition 'xilinx.com:interface:axis:1.0' (from Xilinx Repository). INFO: [IP_Flow 19-5107] Inferred bus interface 'output_axis' of definition 'xilinx.com:interface:axis:1.0' (from Xilinx Repository). INFO: [IP_Flow 19-5107] Inferred bus interface 'rstn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). INFO: [IP_Flow 19-4728] Bus Interface 'rstn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. INFO: [IP_Flow 19-4728] Bus Interface 'clk': Added interface parameter 'ASSOCIATED_BUSIF' with value 'input_0_axis'. INFO: [IP_Flow 19-4728] Bus Interface 'clk': Added interface parameter 'ASSOCIATED_RESET' with value 'rstn'. INFO: [IP_Flow 19-818] Not transferring value dependency attribute "(spirit:decode(id('MODELPARAM_VALUE.DATA_WIDTH')) > 8)" into user parameter "KEEP_ENABLE". INFO: [IP_Flow 19-818] Not transferring value dependency attribute "(spirit:decode(id('MODELPARAM_VALUE.DATA_WIDTH')) / 8)" into user parameter "KEEP_WIDTH". WARNING: [IP_Flow 19-533] HDL Parameter 'KEEP_ENABLE (Keep Enable)': Missing data type WARNING: [IP_Flow 19-11770] Clock interface 'clk' has no FREQ_HZ parameter. INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis' of definition 'xilinx.com:interface:axis:1.0' (from Xilinx Repository). INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis' of definition 'xilinx.com:interface:axis:1.0' (from Xilinx Repository). INFO: [IP_Flow 19-5107] Inferred bus interface 'aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). INFO: [IP_Flow 19-5107] Inferred bus interface 'aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository). INFO: [IP_Flow 19-4728] Bus Interface 'aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. INFO: [IP_Flow 19-4728] Bus Interface 'aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 'm_axis'. INFO: [IP_Flow 19-4728] Bus Interface 'aclk': Added interface parameter 'ASSOCIATED_RESET' with value 'aresetn'. WARNING: [IP_Flow 19-11770] Clock interface 'aclk' has no FREQ_HZ parameter. INFO: [IP_Flow 19-1976] HDL Parser: Replacing 'InitialValue' by 1 for port or parameter 'LFSR' INFO: [IP_Flow 19-5107] Inferred bus interface 'ACLK' of definition 'xilinx.com:signal:clock:1.0' (from X_INTERFACE_INFO parameter from HDL file). INFO: [IP_Flow 19-5107] Inferred bus interface 'ACLK' of definition 'xilinx.com:signal:clock:1.0' (from 'X_INTERFACE_INFO' attribute). INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis' of definition 'xilinx.com:interface:axis:1.0' (from Xilinx Repository). INFO: [IP_Flow 19-5107] Inferred bus interface 'aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository). INFO: [IP_Flow 19-4728] Bus Interface 'aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'. INFO: [IP_Flow 19-4728] Bus Interface 'ACLK': Added interface parameter 'ASSOCIATED_BUSIF' with value 'm_axis'. INFO: [IP_Flow 19-4728] Bus Interface 'ACLK': Added interface parameter 'ASSOCIATED_RESET' with value 'aresetn'. WARNING: [IP_Flow 19-11770] Clock interface 'ACLK' has no FREQ_HZ parameter. ERROR: [IP_Flow 19-3478] Validation failed for parameter 'M00 TDATA Remap String(M00_TDATA_REMAP)' with value 'tdata[31:0]' for BD Cell 'axis_broadcaster_0'. Validation failed for parameter 'M00 TDATA Remap String(M00_TDATA_REMAP)' with value 'tdata[31:0]' for BD Cell 'axis_broadcaster_0'. Range specification exceeds input signal width (8): tdata[31:0],Error: element tdata[31:0] makes remap too large!
ERROR: [IP_Flow 19-3478] Validation failed for parameter 'M01 TDATA Remap String(M01_TDATA_REMAP)' with value 'tdata[31:0]' for BD Cell 'axis_broadcaster_0'. Validation failed for parameter 'M01 TDATA Remap String(M01_TDATA_REMAP)' with value 'tdata[31:0]' for BD Cell 'axis_broadcaster_0'. Range specification exceeds input signal width (8): tdata[31:0],Error: element tdata[31:0] makes remap too large!
INFO: [IP_Flow 19-3438] Customization errors found on 'axis_broadcaster_0'. Restoring to previous valid configuration. INFO: [Common 17-17] undo 'set_property' ERROR: [Common 17-39] 'set_property' failed due to earlier errors.
"rdi::add_properties -dict {CONFIG.M00_TDATA_REMAP {tdata[31:0]} CONFIG.M01_TDATA_REMAP {tdata[31:0]}} /axis_broadcaster_0" invoked from within "set_property -dict [list CONFIG.M00_TDATA_REMAP {tdata[31:0]} CONFIG.M01_TDATA_REMAP {tdata[31:0]} ] $axis_broadcaster_0" (procedure "cr_bd_DDC_Block" line 253) invoked from within "cr_bd_DDC_Block """ (file "create_saturn_project.tcl" line 1090) update_compile_order -fileset sources_1
Appreciate your help