Zero-width bitvectors are not supported by the Fixed-Size Bitvector theory in SMT, but Std.BitVec allows them. This can cause interesting issues. Here is a motivating example.
The following is a theorem in Lean:
∀ (x : BitVec 8), x ++ (Std.BitVec.ofNat 0 0) = x
When auto is used to prove the theorem above, (Std.BitVec.ofNat 0 0) is translated to a 1-bit SMT bitvector, and a sort mismatch error is obtained from the solver (log below).
Perhaps a simplification rule is needed to tackle this case?
Zero-width bitvectors are not supported by the Fixed-Size Bitvector theory in SMT, but
Std.BitVec
allows them. This can cause interesting issues. Here is a motivating example.The following is a theorem in Lean:
∀ (x : BitVec 8), x ++ (Std.BitVec.ofNat 0 0) = x
When auto is used to prove the theorem above,
(Std.BitVec.ofNat 0 0)
is translated to a 1-bit SMT bitvector, and a sort mismatch error is obtained from the solver (log below).Perhaps a simplification rule is needed to tackle this case?