ODIN: module and model name collisions

If a model from the arch file and a module from the verilog have the same name, 
then odin outputs a blif that has multiple .models with the same name, and this 
causes a parse error, in ABC for example.

Say, if you use this verilog, with something that has a carry chain called 
"adder":

`define ADDER_WIDTH 5

module adder (clk, a, b, sum);
    input clk;
    input  [`ADDER_WIDTH-1:0] a;
    input  [`ADDER_WIDTH-1:0] b;
    output [`ADDER_WIDTH  :0] sum;
    reg    [`ADDER_WIDTH  :0] sum;

    always @(posedge clk) begin
        sum <= a + b;
    end

endmodule

then this happens in the .blif:

.model adder
.inputs top^clk top^a~0 top^a~1 top^a~2 top^a~3 top^a~4 top^b~0 top^b~1 top^b~2 
\
 top^b~3 top^b~4
.outputs top^sum~0 top^sum~1 top^sum~2 top^sum~3 top^sum~4 top^sum~5

... blif ...

.subckt adder ...

... blif ...

.model adder
.inputs  a[0]  a[1]  a[2]  a[3]  b[0]  b[1]  b[2]  b[3]  cin[0]
.outputs cout[0] sumout[0] sumout[1] sumout[2] sumout[3]
.blackbox
.end

and then ABC complains:

Line <linenum of first .subckt adder> : The number of ports (14) in .subckt 
differs from the sum of PIs and POs of the model (17).
Reading network from file has failed.

Attached are the files used and produced

Original issue reported on code.google.com by walkerm...@gmail.com on 9 Jul 2014 at 10:20

Attachments:

leekeith / vtr-verilog-to-routing

ODIN: module and model name collisions #91