ksstms
commented
3 years ago Pins
The SIOC clock line is always driven by the master, so no tri-state logic is necessary.
The SIOD data line is open collector. This will be driven using a tri-state output buffer (OBUFT) in the FPGA. We don't want to put that in our module, so the SCCB module will have siod_o and siod_t outputs, and siod_i input. To implement the open collector output, we can keep siod_o at constant 0, and only control the siod_t signal.
Protocol
Paste the following code here. As you can see, we have 3 types of transactions. The '?' bits don't really matter for us, because (in theory) they are either don't-care or driven to 1 by the master. When the master is active, the data is shifted out bit-by-bit. When the slave is active the data bits are shifted in.
Spoiler: WaveDrom code
``` {signal: [ ['Write reg', {name: 'sioc', wave: '1.0.1.0.1.0.1.0.1.0.1.0.1.0.1.0.1.0.1.0.1.0.1.0.1.0.1......'}, {name: 'siod_t', wave: '10.3...3...3...1...4...4...4...1...5...5...5...1...0.1.....', data: ['A7', '...', 'A0', 'R7', '...', 'R0', 'V7', '...', 'V0','...', 'r0']}, {name: 'siod_i', wave: '10.3...3...3...8...4...4...4...8...5...5...5...8...0.1.....', data: ['A7', '...', 'A0', '?', 'R7', '...', 'R0', '?', 'V7', '...', 'V0', '?']}, ], {name: ''}, ['Set read address', {name: 'sioc', wave: '1.0.1.0.1.0.1.0.1.0.1.0.1.0.1.0.1.0.1.....'}, {name: 'siod_t', wave: '10.3...3...3...1...4...4...4...1...0.1....', data: ['A7', '...', 'A0', 'R7','...','R0']}, {name: 'siod_i', wave: '10.3...3...3...8...4...4...4...8...0.1....', data: ['A7', '...', 'A0', '?','R7','...','R0','?']}, ], {name: ''}, ['Read reg', {name: 'sioc', wave: '1.0.1.0.1.0.1.0.1.0.1.0.1.0.1.0.1.0.1.....'}, {name: 'siod_t', wave: '10.3...3...3...1...................0.1....', data: ['A7', '...', 'A0', 'V7','...', 'V0']}, {name: 'siod_i', wave: '10.3...3...3...8...5...5...5...8...0.1....', data: ['A7', '...', 'A0', '?','V7','...','V0','?']}, ], ]} ```Implementation idea
In order to make this design small, we can use a single shift register for both the output and the input.
- between a falling and a rising edge: copy the MSB of the register to the output register
- between a rising and a falling edge: shift the register up, and bring in the input bit.
- after the transaction is done, we can filter the responses from the shift register.
The Control block needs 2 counters. One for timing the events, and one for counting the bits.
Old OmniVision sensors (including the OV7670) use the SCCB interface instead of I2C. It's basically the same, but the ACK bit is don't-care, and the SCL line is not open collector (always driven by the master).
Unfortunately, neither Zynq PS IIC nor AXI IIC can deal with this, so let's create our own SCCB module. Here's the specification.
This should be a lot easier than implementing IIC.