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legokor / FPGA-Utils

Little modules that make life easier
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Clock domain crossing #4

Closed ksstms closed 3 years ago

ksstms commented 3 years ago

Synchronize a signal to a clock. The width and the synchronization stages should be parameters of the module.

ksstms commented 3 years ago

example: ( ASYNC_REG="true" ) reg [WIDTH-1:0] foo [STAGES-1:0];

ksstms commented 3 years ago

It's good, but let's change the default WIDTH to 1, because that's the most common use case.