I was wondering if just changing col and row decoder should be sufficient to change the current chip from single access to parallel compute application of the chip? or column mux design also needs to be changed? I am sensing only via current flowing in columns for MAC operations.
Could I request a schematic for the col and row decoder ,col mux for better understanding?
I was wondering if just changing col and row decoder should be sufficient to change the current chip from single access to parallel compute application of the chip? or column mux design also needs to be changed? I am sensing only via current flowing in columns for MAC operations. Could I request a schematic for the col and row decoder ,col mux for better understanding?