understanding the sensing scheme

[Samarthjainabout]

Hi As per openram documents, the sensing circuit has BL and BL bar which it senses but in reram case there is no BL bar. I wanted to check if in this open-reram git, are bl and bl bar same and shorted ? and if so why are we doing double reading from same bit cell? To me it looks like a 1T1R Reram cell?

BITCELL

[lekez2005]

The sense amp used in OpenRAM is differential, as you can see in the image you posted. Differential sense amps are generally faster but need you to save both data and data_bar, which CMOS 6T SRAM does. However, ReRAM only stores data, so the sense amp must be single-ended.

https://github.com/lekez2005/opennvram-reram/blob/main/technology/sky130/sp_lib/re_ram_sense_amp.sp shows the spice netlist including transistor parameters. Here is the equivalent image in schematic form:

[Samarthjainabout]

why there are two BL then from same Reram T cell then as shown in above layout ? is it just to reduce resistance ?

[lekez2005]

That's for write purposes. Only BL is used for read

[Samarthjainabout]

Hi, If the sensing is single ended then why still do you need a precharge circuit? Is it not to charge the BL and BL bar when we read sram, the lines current is mismatched and that's how we sense for SRAM? in Reram I am not sure how you might be using it? Can you kindly explain or share the schematic of its use here?

[lekez2005]

Here is the schematic of the precharge cell, which is really more of a discharge cell

During sensing, only br_reset is enabled. The full sensing scheme looks like:

[Samarthjainabout]

could I ask what is the function of Vclamp and Vclampp?are Are they for dc biasing of input of comparator gate?

[lekez2005]

vclamp clamps the maximum voltage across the ReRAM cell during reads to minimize read disturb. The combination of vclamp and vclampp regulates the current through the ReRAM cell and yes, also DC biasing. Sample values for both here: https://github.com/lekez2005/opennvram-reram/blob/488853aa7b52478904c9fb38f9a8673cde1e10e4/compiler/tests/reram/config_reram_sky130.py#L68

[Samarthjainabout]

Here is the schematic of the precharge cell, which is really more of a discharge cell

During sensing, only br_reset is enabled. The full sensing scheme looks like:

how is bl_reset used ?in what cases?

[lekez2005]

bl_reset is technically not strictly necessary. In the current implementation, it is used during the first half of write operations to equalize the bitlines. More information about this and other control signals can be gleaned at https://github.com/lekez2005/opennvram-reram/blob/488853aa7b52478904c9fb38f9a8673cde1e10e4/compiler/modules/reram/reram_control_buffers.py#L22

[Samarthjainabout]

So for example we set the device, BR_reset GROUNDS the row and we apply pulse from BL write driver .Other case when we reset the device we use BL_Reset to ground the BL and apply pulse from BR write driver? thats what you mean by equalize the bitlines?

[Samarthjainabout]

vclamp clamps the maximum voltage across the ReRAM cell during reads to minimize read disturb. The combination of vclamp and vclampp regulates the current through the ReRAM cell and yes, also DC biasing. Sample values for both here:

https://github.com/lekez2005/opennvram-reram/blob/488853aa7b52478904c9fb38f9a8673cde1e10e4/compiler/tests/reram/config_reram_sky130.py#L68

I am a bit confused about how vclamp is helping in read disturb. if the read voltage is applied from BL and if it is more than vclamp -VTh ,it disconnect only read circuit from rram by turning off vclamp fet? other possibility is while u r changing vclampp for pmos to tune the read current, u r using below nmos as safety incase voltage is raised too much? I also mean that read disturb can come from BL from nearby cell only but BL point is not clampped and still causes read disturb?

[lekez2005]

So for example we set the device, BR_reset GROUNDS the row and we apply pulse from BL write driver .Other case when we reset the device we use BL_Reset to ground the BL and apply pulse from BR write driver? thats what you mean by equalize the bitlines?

No bl_reset and br_reset are only active during the first half of the cycles. The write drivers themselves drive to ground or bitline voltage. bl_reset is more useful for unselected columns (either more than one word per row or mask bit is not selected) to prevent spurious instantaneous currents ( and minimize write disturb) when the wordline driver is activated.

[lekez2005]

vclamp clamps the maximum voltage across the ReRAM cell during reads to minimize read disturb. The combination of vclamp and vclampp regulates the current through the ReRAM cell and yes, also DC biasing. Sample values for both here: https://github.com/lekez2005/opennvram-reram/blob/488853aa7b52478904c9fb38f9a8673cde1e10e4/compiler/tests/reram/config_reram_sky130.py#L68

I am a bit confused about how vclamp is helping in read disturb. if the read voltage is applied from BL and if it is more than vclamp -VTh ,it disconnect only read circuit from rram by turning off vclamp fet? other possibility is while u r changing vclampp for pmos to tune the read current, u r using below nmos as safety incase voltage is raised too much? I also mean that read disturb can come from BL from nearby cell only but BL point is not clampped and still causes read disturb?

I don't fully understand what you mean. but this part about "if the read voltage is applied from BL and if it is more than vclamp -VTh ,it disconnect only read circuit from rram by turning off vclamp fet" is what I was going for with this design