Initial support for testing power domains

[leonardt]

This adds a PowerTester class that adds the methods:

• add_power - marks a port to be generated as supply1
• add_ground - marks a port to be generated as supply0
• add_tri - marks a port to be generated as tri

When the Tester is compiled to a SV test bench, the marked ports are generated as the specified type (as opposed to the default behavior with reg for inputs and wire for outputs)

[coveralls]

Pull Request Test Coverage Report for Build 944

• 31 of 32 (96.88%) changed or added relevant lines in 3 files are covered.
• No unchanged relevant lines lost coverage.
• Overall coverage increased (+4.7%) to 81.047%

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Changes Missing Coverage	Covered Lines	Changed/Added Lines	%
fault/system_verilog_target.py	13	14	92.86%
<!--	Total:	31	32	96.88%	-->

Totals
Change from base Build 937:	4.7%
Covered Lines:	1471
Relevant Lines:	1815

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💛 - Coveralls