Explicitly set integer literal size in SV backend

[leonardt]

Fixes issue introduced in https://github.com/StanfordAHA/lassen/pull/95 where a 66 bit constant value was generated in system verilog and ncsim complained with:

inst = 21040819108348690454;
--
  | \|
  | ncvlog: *W,INTOVF (WrappedPE_tb.sv,37\|34): bit overflow during conversion from text [2.5(IEEE)] (32 bits).

This changes the system verilog backend to always emit the size of the integer literal using the <size>'d<value> syntax.

[coveralls]

Pull Request Test Coverage Report for Build 950

• 0 of 4 (0.0%) changed or added relevant lines in 1 file are covered.
• No unchanged relevant lines lost coverage.
• Overall coverage decreased (-0.1%) to 76.254%

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Changes Missing Coverage	Covered Lines	Changed/Added Lines	%
fault/system_verilog_target.py	0	4	0.0%
<!--	Total:	0	4	0.0%	-->

Totals
Change from base Build 945:	-0.1%
Covered Lines:	1368
Relevant Lines:	1794

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💛 - Coveralls