Closed leonardt closed 5 years ago
Changes Missing Coverage | Covered Lines | Changed/Added Lines | % | ||
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fault/system_verilog_target.py | 6 | 14 | 42.86% | ||
<!-- | Total: | 6 | 14 | 42.86% | --> |
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Change from base Build 1029: | -0.3% |
Covered Lines: | 1392 |
Relevant Lines: | 1832 |
Addresses issue where
ncsim
will not recompile a test bench if the new test bench file is generated within 1 second of the previous test bench file, see https://github.com/StanfordAHA/lassen/issues/111.This forces fault to, by default, check whether the test bench exists, if so, diff the modification timestamp on the new file with the old file. if the new file is less than or equal (handling the case when this happens multiple times in a row), fault sets the new file to be "newer" than the old file.