Should the tutorial be changed? Am I using the command wrong. I would prefer not to have to manually compile my module before using fault. However, without those lines, I need the following message that indicates a lack of compilation.
Users/durst/anaconda/envs/aetherling/bin/python "/Users/durst/Library/Application Support/JetBrains/Toolbox/apps/PyCharm-P/ch-0/183.4886.43/PyCharm.app/Contents/helpers/pycharm/_jb_pytest_runner.py" --target test_rshift.py::test_rshift_parallel -- -s
Launching pytest with arguments -s test_rshift.py::test_rshift_parallel in /Users/durst/dev/W17-8/aetherling/tests
/Users/durst/anaconda/envs/aetherling/lib/python3.7/site-packages/pysmt/walkers/generic.py:43: DeprecationWarning: Using or importing the ABCs from 'collections' instead of from 'collections.abc' is deprecated, and in 3.8 it will stop working
if len(nodetypes) == 1 and isinstance(nodetypes[0], collections.Iterable):
============================= test session starts ==============================
platform darwin -- Python 3.7.1, pytest-4.4.1, py-1.8.0, pluggy-0.9.0
rootdir: /Users/durst/dev/W17-8/aetherling
plugins: xdist-1.28.0, forked-1.0.2collected 1 item
test_rshift.py F
tests/test_rshift.py:7 (test_rshift_parallel)
def test_rshift_parallel():
width = 5
num_in = 4
test_vals = [2,5,3,8]
shift_amount = 2
in_type = Array[num_in, Array[width, In(BitIn)]]
args = ['I', in_type, 'O', Out(in_type)] + ClockInterface(False, False)
testcircuit = DefineCircuit('Test', *args)
rshift = RShiftParallel(num_in, shift_amount, in_type.T)
wire(rshift.I, testcircuit.I)
wire(testcircuit.O, rshift.O)
EndCircuit()
#magma.compile("vBuild/" + testcircuit.name, testcircuit, output="coreir-verilog",
# passes=["rungenerators", "wireclocks-coreir", "verifyconnectivity --noclkrst", "flattentypes", "flatten", "verifyconnectivity --noclkrst", "deletedeadinstances"],
# namespaces=["aetherlinglib", "commonlib", "mantle", "coreir", "global"])
tester = fault.Tester(testcircuit, testcircuit.CLK)
for i, val in enumerate(test_vals):
tester.circuit.I[i] = val
tester.eval()
for i, val in enumerate(test_vals[shift_amount:]):
tester.circuit.O[i + shift_amount].expect(test_vals[i])
> tester.compile_and_run(target="verilator", skip_compile=True, directory="vBuild/")
test_rshift.py:35:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
../../fault/fault/tester.py:211: in compile_and_run
self._compile(target, **kwargs)
../../fault/fault/tester.py:177: in _compile
self.targets[target] = self.make_target(target, **kwargs)
../../fault/fault/tester.py:77: in make_target
return VerilatorTarget(self._circuit, **kwargs)
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
self = <fault.verilator_target.VerilatorTarget object at 0x111230b00>
circuit = Test = DefineCircuit("Test", "I", Array[4, Array[5, In(Bit)]], "O", Array[4, Array[5, Out(Bit)]], "CLK", In(Clock))
RS...el_n4_amt2_T_rvArray_5_In_Bit___inst0.I)
wire(RShiftParallel_n4_amt2_T_rvArray_5_In_Bit___inst0.O, Test.O)
EndCircuit()
directory = '/Users/durst/dev/W17-8/aetherling/tests/vBuild/', flags = []
skip_compile = True, include_verilog_libraries = [], include_directories = []
magma_output = 'coreir-verilog', circuit_name = None, magma_opts = {}
skip_verilator = False
def __init__(self, circuit, directory="build/",
flags=[], skip_compile=False, include_verilog_libraries=[],
include_directories=[], magma_output="coreir-verilog",
circuit_name=None, magma_opts={}, skip_verilator=False):
"""
Params:
`include_verilog_libraries`: a list of verilog libraries to include
with the -v flag. From the verilator docs:
-v <filename> Verilog library
`include_directories`: a list of directories to include using the
-I flag. From the the verilator docs:
-I<dir> Directory to search for includes
"""
super().__init__(circuit, circuit_name, directory, skip_compile,
include_verilog_libraries, magma_output, magma_opts)
self.flags = flags
self.include_directories = include_directories
# Compile the design using `verilator`, if not skip
if not skip_verilator:
driver_file = self.directory / Path(
f"{self.circuit_name}_driver.cpp")
verilator_cmd = verilator_utils.verilator_cmd(
self.circuit_name, self.verilog_file.name,
self.include_verilog_libraries, self.include_directories,
driver_file.name, self.flags)
result = self.run_from_directory(verilator_cmd)
log(logging.info, result.stdout.decode())
log(logging.info, result.stderr.decode())
if result.returncode:
> raise Exception(f"Running verilator cmd {verilator_cmd} failed:"
f" {result.stderr.decode()}")
E Exception: Running verilator cmd verilator -Wall -Wno-INCABSPATH -Wno-DECLFILENAME --cc Test.v --exe Test_driver.cpp --top-module Test failed: %Error: Cannot find file containing module: Test.v
E %Error: This may be because there's no search path specified with -I<dir>.
E %Error: Looked in:
E %Error: Test.v
E %Error: Test.v.v
E %Error: Test.v.sv
E %Error: obj_dir/Test.v
E %Error: obj_dir/Test.v.v
E %Error: obj_dir/Test.v.sv
E %Error: Exiting due to 9 error(s)
E %Error: Command Failed /usr/local/Cellar/verilator/4.014/bin/verilator_bin -Wall -Wno-INCABSPATH -Wno-DECLFILENAME --cc Test.v --exe Test_driver.cpp --top-module Test
../../fault/fault/verilator_target.py:125: Exception
The tutorial says
compile_and_runwill compile my module. However, I also needed the below lines to actually compile my module https://github.com/David-Durst/aetherling/blob/6de744252d7b5becb9be41e7b452a7e21a8a1fc5/tests/test_rshift.py#L24-L26.Should the tutorial be changed? Am I using the command wrong. I would prefer not to have to manually compile my module before using fault. However, without those lines, I need the following message that indicates a lack of compilation.