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leonardt / fault

A Python package for testing hardware (part of the magma ecosystem)
BSD 3-Clause "New" or "Revised" License
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Define variables and wait_until_(high|low|posedge|negedge) #141

Closed sgherbst closed 5 years ago

sgherbst commented 5 years ago

Depends on pull request #139

  1. Define variables can now be specified to a SystemVerilogTarget via the defines argument. This can be a convenient manner to pass arguments into existing verilog code.
  2. Added a test for the while loop functionality in fault (tests/test_while_loop.py)
  3. Added support for UnaryOp to SystemVerilogTarget.
  4. Added wait_until_high/wait_until_low/wait_until_posedge/wait_until_negedge into the Tester. These are not implemented as actions but instead are built from the _while() and step() commands.