Closed sgherbst closed 5 years ago
The tests seem to be failing for a similar reason as in pull request #143. Doesn't seem to be related to the content of the PR because the build is crashing before getting to pytest.
Closing since these changes are included in PR #148
This PR allows a user to run an existing (presumably hand-written) SystemVerilog testbench using fault. In this case, fault is essentially being using for its capability to abstract simulator commands over ncsim, vcs, and iverilog. However, this is still a useful capability in its own right, and might be a stepping stone for the user to get started creating their own testbenches using the full power of fault.
The following features are included: