Closed leonardt closed 4 years ago
Failed GarnettFlow because I was merging branches at the exact same time.
I'm trying the fix and still getting the same issue as before:
From running file: https://github.com/David-Durst/aetherling/blob/9fc6ade1928b2a6d428000e5e88d744c77031b34/aetherling/examples/ae_circuit13356-483_internals.py#L88
Traceback (most recent call last):
File "/home/david/.local/share/JetBrains/Toolbox/apps/PyCharm-P/ch-0/192.6262.63/helpers/pydev/pydevd.py", line 2060, in <module>
main()
File "/home/david/.local/share/JetBrains/Toolbox/apps/PyCharm-P/ch-0/192.6262.63/helpers/pydev/pydevd.py", line 2054, in main
globals = debugger.run(setup['file'], None, None, is_module)
File "/home/david/.local/share/JetBrains/Toolbox/apps/PyCharm-P/ch-0/192.6262.63/helpers/pydev/pydevd.py", line 1405, in run
return self._exec(is_module, entry_point_fn, module_name, file, globals, locals)
File "/home/david/.local/share/JetBrains/Toolbox/apps/PyCharm-P/ch-0/192.6262.63/helpers/pydev/pydevd.py", line 1412, in _exec
pydev_imports.execfile(file, globals, locals) # execute the script
File "/home/david/.local/share/JetBrains/Toolbox/apps/PyCharm-P/ch-0/192.6262.63/helpers/pydev/_pydev_imps/_pydev_execfile.py", line 18, in execfile
exec(compile(contents+"\n", file, 'exec'), glob, loc)
File "/home/david/dev/aetherling/aetherling/examples/ae_circuit13356-483.py", line 105, in <module>
fault_helpers.compile_and_run(tester)
File "/home/david/dev/aetherling/aetherling/helpers/fault_helpers.py", line 87, in compile_and_run
}, directory="vBuild/", flags=["-Wno-fatal"])
File "/home/david/dev/fault/fault/tester.py", line 291, in compile_and_run
self._compile_and_run(target=target, **kwargs)
File "/home/david/dev/fault/fault/tester.py", line 276, in _compile_and_run
self.run(target)
File "/home/david/dev/fault/fault/tester.py", line 264, in run
target_obj.run(self.actions, self.verilator_includes)
File "/home/david/dev/fault/fault/verilator_target.py", line 519, in run
_circuit)
File "/home/david/dev/fault/fault/verilator_target.py", line 488, in generate_code
code = self.generate_action_code(i, action)
File "/home/david/dev/fault/fault/verilog_target.py", line 91, in generate_action_code
return self.make_print(i, action)
File "/home/david/dev/fault/fault/verilator_target.py", line 274, in make_print
name = verilator_name(port.name)
File "/home/david/dev/fault/fault/verilator_utils.py", line 71, in verilator_name
name = verilog_name(name)
File "/home/david/dev/fault/fault/verilog_utils.py", line 8, in verilog_name
array_name = verilog_name(name.array.name)
File "/home/david/dev/fault/fault/verilog_utils.py", line 20, in verilog_name
raise NotImplementedError(name, type(name))
NotImplementedError: (Const_tSSeq_8_Int__hasCEFalse_hasResetFalse_hasValidTrue_inst0.O, <class 'magma.ref.InstRef'>)
I'm concerned that I haven't updated fault correctly. Could you try the code on your machine to verify that the issue is not with my version of fault?
I think fault is on the right commit because of the following outputs
(ae2) david@david-VirtualBox:~/dev/aetherling$ pip list
Package Version Location
------------------ --------- --------------------------
...
fault 2.0.16 /home/david/dev/fault
...
(ae2) david@david-VirtualBox:~/dev/fault$ git log --oneline
18892d7 (HEAD -> fix-print-internal, origin/fix-print-internal) Process circuit name before params
Hmm, I had to rebase on https://github.com/leonardt/fault/pull/165 to even run the test, once I did it seems to work without issue for me. Did you perhaps forget to push a change that induced the above error?
(work without issue in that the prints worked, but the test was failing)
Looks like this:
<STDOUT>
clk: 0
output 0.t0: 1
output 0.t1: 10
output 1.t0: 2
output 1.t1: 8
output 2.t0: 3
output 2.t1: 9
output 3.t0: 4
output 3.t1: 3
output 4.t0: 2
output 4.t1: 4
output 5.t0: 1
output 5.t1: 2
output 6.t0: 2
output 6.t1: 2
output 7.t0: 3
output 7.t1: 2
</STDOUT>
<STDERR>
Got : 0x3a
Expected : 0x55
i : 27
Port : Module_3.O[0]
</STDERR>
Oh sorry, I was running the wrong file (didn't include the _internals
suffix)
@David-Durst your issue should be fixed by ff3587edecaf2d4276cbe7e9cd0e5a166483f88c (latest commit on this branch), but it fails later on because the instance you're referring to has been flattened out. However, when I try to turn off flattening, some of the generates aren't being run. Perhaps this is an issue with coreir, can you check with Ross? It seems like you should be able to run the generators you need without flattening everything.
I'm doing the flattening in https://github.com/David-Durst/aetherling/blob/9fc6ade1928b2a6d428000e5e88d744c77031b34/aetherling/helpers/fault_helpers.py#L85. I'll try to turn that off.
Running without the flatten pass produces the following error:
ERROR: In file: vBuild/Module_3.json
Missing Generator Symbol: aetherlinglib.hydrate
It looks like the aetherling CoreIR c++ library isn't being loaded somewhere after the flattening pass. I'll ping Ross about this since he's not taggable in this repo.
@David-Durst, make sure somewhere you are calling the load_lib("aetherling"). That error means that aetherling was not loaded in CoreIR. Make sure that somewhere Context.load_library("aetherling") is being called. If the coreir library is missing, then that call should complain first.
Also, running the generators (the pass "rungenerators") should be called before flattening.
I believe that I'm loading aetherlinglib. If I don't flatten, the aetherling library components are used fine. Additionally, as can be seen below, I'm including the aetherlinglib namespace:
"passes": ["rungenerators", "wireclocks-coreir", "verifyconnectivity --noclkrst", "flattentypes", "verifyconnectivity --noclkrst", "deletedeadinstances"],
"namespaces": ["aetherlinglib", "commonlib", "mantle", "coreir", "global"]
from https://github.com/David-Durst/aetherling/blob/670bdf53c37c5fa107a676cd12f2628fceebf50a/aetherling/helpers/fault_helpers.py#L85-L86 (note: I haven't push my change removing the "flatten" pass. That is just local.)
Hmmm actually looking at the error more closely, it looks like the coreir binary executable is being run on the file vBuild/Module_3.json. The call to the coreir binary needs to explicitly pass in "-l aetherling". Do you know where in the code that is happening?
https://github.com/phanrahan/magma/blob/9d3fef16c29c685ceb7dc9a38cdc6ff66d9c0099/magma/compile.py#L81 is where fault (using magma) compiles the circuit to coreir.
This is the generated command for my failing file:
'coreir -l global,coreir,commonlib,corebit -i vBuild/Module_3.json -o vBuild/Module_3.v --verilator_debug'
It's missing aetherling.
I'm confused slightly.
@leonardt, how do I get aetherlinglib
to be added as a dependency by https://github.com/phanrahan/magma/blob/9d3fef16c29c685ceb7dc9a38cdc6ff66d9c0099/magma/compile.py#L61-L65?
@David-Durst, it works when flattening because aetherling is now not a dependency since there is only one (flattened) module.
Let me summarize some things that occurred that caused this issue.
In coreir, when you load an external library, then call rungenerators; generated modules are defined for all the instances that reference the generators (with the appropriate parameters). These generated modules are stored in that library's namespace. When you serialize the CoreIR to Json, it only serializes modules within namespaces specified with the namespace option (by default it only saves "global"). I suspect that magma is not specifying the namespaces during serialization and therefore the generated aetherling modules are not being saved in the json. Once this happens, in order to translate it to verilog from the json file, aetherling library needs to be reloaded, and generators need to be rerun.
I think if magma wants to keep the code path of first serializing to json, then to verilog (I saw a TODO from @rsetaluri, that this might be changed) then we should serialize to json with all the generated modules from all the namespaces. This might require some updates to pycoreir API which I can look into. @leonardt, @David-Durst, thoughts?
I am specifying the aetherlinglib
namespace at the front. I don't know where the namespaces are being passed to coreir.
What I didn't understand was where aetherlinglib was being loaded. Clearly, the library had to be loaded for part of the process if it worked when flattening.
I think the unflattened flow is the following:
You specify the library to magma. Magma loads the aetherling library via pycoreir. You call "rungenerators" which creates all the modules in the current coreir context. CoreIR's top module is storing instances of generated aetherling modules. You call "compile to verilog". Magma serializes the coreir context to a json file. It includes your top level module, but probably not the generated aetherling modules which you instance from your top module (see previous comment). Magma then calls out to the shell to run the coreir binary on that json file. The coreir binary creates a separate coreir context (different than the magma one) with aetherling not loaded.
The flattened flow is the same except now there are no instances of aetherling modules in the coreir json file. Thus there is no dependency on aetherling when you run the coreir binary on it.
@David-Durst does this make sense?
Yes, that makes sense. Now the coreir binary needs to have the flag passed to it for loading the aetherlinglib. https://github.com/phanrahan/magma/blob/9d3fef16c29c685ceb7dc9a38cdc6ff66d9c0099/magma/compile.py#L61-L65 does this, but I don't think it knows about aetherlinglib.
This https://github.com/phanrahan/magma/pull/442 forwards the namespaces in the namespace
parameter to the coreir verilog command, avoiding the error related to running the aetherling generator. Now i'm getting
ERROR: Cannot select out_0 From hydrate_tArray_8_Array_8_Bit___inst0
Type: {'in':BitIn[64], 'out':Bit[8][8]}
0 libcoreir.dylib 0x000000010b73deec _ZN6CoreIR8Wireable3selERKNSt3__112basic_stringIcNS1_11char_traitsIcEENS1_9allocatorIcEEEE + 284
1 libcoreir.dylib 0x000000010b657f88 _ZN6CoreIR9ModuleDef3selERKNSt3__15dequeINS1_12basic_stringIcNS1_11char_traitsIcEENS1_9allocatorIcEEEENS6_IS8_EEEE + 184
2 libcoreir.dylib 0x000000010b657c8f _ZN6CoreIR9ModuleDef3selERKNSt3__112basic_stringIcNS1_11char_traitsIcEENS1_9allocatorIcEEEE + 191
3 libcoreir.dylib 0x000000010b5c0159 _ZN6CoreIR12loadFromFileEPNS_7ContextENSt3__112basic_stringIcNS2_11char_traitsIcEENS2_9allocatorIcEEEEPPNS_6ModuleE + 28745
4 coreir 0x000000010b377cbb main + 9963
5 libdyld.dylib 0x00007fff590943d5 start + 1
6 ??? 0x0000000000000008 0x0 + 8
when inspecting the output json
file, it seems like the output type of the hydrate instances has been flattened, while the input type hasn't, but the invocation of coreir is expecting the unflattened version. Perhaps we need to flatten before calling the verilog compile again?
Running https://github.com/David-Durst/aetherling/blob/aa4e1101f77c9e29b682d8aa108755978cd02b13/aetherling/examples/ae_circuit13356-483_internals.py without flatten pass with flattentypes produces
/Users/durst/anaconda/envs/aetherling/bin/python /Users/durst/dev/W17-8/aetherling/aetherling/examples/ae_circuit13356-483_internals.py
/Users/durst/anaconda/envs/aetherling/lib/python3.7/site-packages/pysmt/walkers/generic.py:43: DeprecationWarning: Using or importing the ABCs from 'collections' instead of from 'collections.abc' is deprecated, and in 3.8 it will stop working
if len(nodetypes) == 1 and isinstance(nodetypes[0], collections.Iterable):
/Users/durst/anaconda/envs/aetherling/lib/python3.7/site-packages/pysmt/walkers/generic.py:43: DeprecationWarning: Using or importing the ABCs from 'collections' instead of from 'collections.abc' is deprecated, and in 3.8 it will stop working
if len(nodetypes) == 1 and isinstance(nodetypes[0], collections.Iterable):
ERROR: Cannot select out_0 From hydrate_tArray_8_Array_8_Bit___inst0
Type: {'in':BitIn[64], 'out':Bit[8][8]}
0 libcoreir.dylib 0x00000001081b8bfc _ZN6CoreIR8Wireable3selERKNSt3__112basic_stringIcNS1_11char_traitsIcEENS1_9allocatorIcEEEE + 284
1 libcoreir.dylib 0x00000001080d0a11 _ZN6CoreIR9ModuleDef3selERKNSt3__15dequeINS1_12basic_stringIcNS1_11char_traitsIcEENS1_9allocatorIcEEEENS6_IS8_EEEE + 177
2 libcoreir.dylib 0x00000001080d071f _ZN6CoreIR9ModuleDef3selERKNSt3__112basic_stringIcNS1_11char_traitsIcEENS1_9allocatorIcEEEE + 191
3 libcoreir.dylib 0x00000001080372cb _ZN6CoreIR12loadFromFileEPNS_7ContextENSt3__112basic_stringIcNS2_11char_traitsIcEENS2_9allocatorIcEEEEPPNS_6ModuleE + 28715
4 coreir 0x0000000107de5cc3 main + 9587
5 libdyld.dylib 0x00007fff610093d5 start + 1
6 ??? 0x0000000000000008 0x0 + 8
Process finished with exit code 0
Running it without both flatten and flattentypes runs but I don't know how to access the internal port for printing. To get it to run, I had to disable these two lines: https://github.com/David-Durst/aetherling/blob/aa4e1101f77c9e29b682d8aa108755978cd02b13/aetherling/examples/ae_circuit13356-483_internals.py#L101-L102.
However, i'm not sure if that is supposed to work. When I run https://github.com/David-Durst/aetherling/blob/aa4e1101f77c9e29b682d8aa108755978cd02b13/aetherling/examples/ae_circuit24998-6.py without flatten and flattentypes, I get the following error message:
/Users/durst/anaconda/envs/aetherling/bin/python /Users/durst/dev/W17-8/aetherling/aetherling/examples/ae_circuit24998-6.py
/Users/durst/anaconda/envs/aetherling/lib/python3.7/site-packages/pysmt/walkers/generic.py:43: DeprecationWarning: Using or importing the ABCs from 'collections' instead of from 'collections.abc' is deprecated, and in 3.8 it will stop working
if len(nodetypes) == 1 and isinstance(nodetypes[0], collections.Iterable):
/Users/durst/anaconda/envs/aetherling/lib/python3.7/site-packages/pysmt/walkers/generic.py:43: DeprecationWarning: Using or importing the ABCs from 'collections' instead of from 'collections.abc' is deprecated, and in 3.8 it will stop working
if len(nodetypes) == 1 and isinstance(nodetypes[0], collections.Iterable):
/Users/durst/dev/W17-8/coreir/2coreir/src/binary/coreir.cpp:187 Running Runningvpasses
:114 Running Pass: rungenerators
:10 In Run Generators
:26 :114 Running Pass: verifyinputconnections
:114 Running Pass: removebulkconnections
:114 Running Pass: verifyinputconnections
:114 Running Pass: createinstancegraph
:114 Running Pass: flattentypes
ERROR: NYI flatten types of generator or nodef module
{global.Term_Tuple_lane_Array_2_Bit__val_Array_50_Array_8_Bit___t}.I Is not a flattened type!
Type is: {'lane':BitIn[2], 'val':BitIn[8][50]}
0 libcoreir.dylib 0x00000001077dc256 _ZN6CoreIR6Passes12FlattenTypes22runOnInstanceGraphNodeERNS_17InstanceGraphNodeE + 278
1 libcoreir.dylib 0x00000001074cf073 _ZN6CoreIR11PassManager20runInstanceGraphPassEPNS_4PassE + 451
2 libcoreir.dylib 0x00000001074cf703 _ZN6CoreIR11PassManager7runPassEPNS_4PassERNSt3__16vectorINS3_12basic_stringIcNS3_11char_traitsIcEENS3_9allocatorIcEEEENS8_ISA_EEEE + 1075
3 libcoreir.dylib 0x00000001074d1031 _ZN6CoreIR11PassManager3runERNSt3__16vectorINS1_12basic_stringIcNS1_11char_traitsIcEENS1_9allocatorIcEEEENS6_IS8_EEEESA_ + 1969
4 libcoreir.dylib 0x0000000107315e28 _ZN6CoreIR7Context9runPassesENSt3__16vectorINS1_12basic_stringIcNS1_11char_traitsIcEENS1_9allocatorIcEEEENS6_IS8_EEEESA_ + 136
5 coreir 0x000000010718019c main + 14924
6 libdyld.dylib 0x00007fff610093d5 start + 1
7 ??? 0x0000000000000008 0x0 + 8
Traceback (most recent call last):
Running command: verilator -Wall -Wno-INCABSPATH -Wno-DECLFILENAME -Wno-fatal --cc Module_4.v --exe Module_4_driver.cpp --top-module Module_4
<STDERR>
%Error: Specified --top-module 'Module_4' was not found in design.
%Error: Exiting due to 1 error(s)
%Error: Command Failed /usr/local/Cellar/verilator/4.014/bin/verilator_bin -Wall -Wno-INCABSPATH -Wno-DECLFILENAME -Wno-fatal --cc Module_4.v --exe Module_4_driver.cpp --top-module Module_4
File "/Users/durst/dev/W17-8/aetherling/aetherling/examples/ae_circuit24998-6.py", line 135, in <module>
</STDERR> fault_helpers.compile_and_run(tester)
File "/Users/durst/dev/W17-8/aetherling/aetherling/helpers/fault_helpers.py", line 99, in compile_and_run
}, directory="vBuild/", flags=["-Wno-fatal"])
Found 1 error(s): File "/Users/durst/dev/W17-8/fault/fault/tester.py", line 302, in compile_and_run
self._compile_and_run(target=target, **kwargs)
File "/Users/durst/dev/W17-8/fault/fault/tester.py", line 286, in _compile_and_run
1) Got return code 10. self._compile(target, **kwargs)
File "/Users/durst/dev/W17-8/fault/fault/tester.py", line 249, in _compile
self.targets[target] = self.make_target(target, **kwargs)
File "/Users/durst/dev/W17-8/fault/fault/tester.py", line 96, in make_target
return VerilatorTarget(self._circuit, **kwargs)
File "/Users/durst/dev/W17-8/fault/fault/verilator_target.py", line 127, in __init__
disp_type=self.disp_type)
File "/Users/durst/dev/W17-8/fault/fault/subprocess_run.py", line 142, in subprocess_run
raise AssertionError
AssertionError
Process finished with exit code 1
I'm using the latest commit from CoreIR dev
commit 3ed48f3ed0282f307d16c7e0e10f35e213e52cef (HEAD -> dev, upstream/dev)
Merge: 3e79a358 900760eb
Author: Ross Daly <rdaly525@stanford.edu>
Date: Tue Oct 8 14:15:14 2019 -0700
Merge pull request #798 from rdaly525/rm-ubuf-master
Rm ubuf master
and the latest from https://github.com/phanrahan/magma/pull/442
With the latest update-json, I get the following with flattentypes
/Users/durst/anaconda/envs/aetherling/bin/python /Users/durst/dev/W17-8/aetherling/aetherling/examples/ae_circuit24998-6.py
/Users/durst/anaconda/envs/aetherling/lib/python3.7/site-packages/pysmt/walkers/generic.py:43: DeprecationWarning: Using or importing the ABCs from 'collections' instead of from 'collections.abc' is deprecated, and in 3.8 it will stop working
if len(nodetypes) == 1 and isinstance(nodetypes[0], collections.Iterable):
/Users/durst/anaconda/envs/aetherling/lib/python3.7/site-packages/pysmt/walkers/generic.py:43: DeprecationWarning: Using or importing the ABCs from 'collections' instead of from 'collections.abc' is deprecated, and in 3.8 it will stop working
if len(nodetypes) == 1 and isinstance(nodetypes[0], collections.Iterable):
ERROR: Cannot select out_bank From hydrate_tTuple_bank_Array_2_Bit__val_Array_50_Array_8_Bit____inst0
Type: {'in':BitIn[402], 'out':{'bank':Bit[2], 'val':Bit[8][50]}}
0 libcoreir.dylib 0x0000000106fcbdbc _ZN6CoreIR8Wireable3selERKNSt3__112basic_stringIcNS1_11char_traitsIcEENS1_9allocatorIcEEEE + 284
1 libcoreir.dylib 0x0000000106ee3d21 _ZN6CoreIR9ModuleDef3selERKNSt3__15dequeINS1_12basic_stringIcNS1_11char_traitsIcEENS1_9allocatorIcEEEENS6_IS8_EEEE + 177
2 libcoreir.dylib 0x0000000106ee3a2f _ZN6CoreIR9ModuleDef3selERKNSt3__112basic_stringIcNS1_11char_traitsIcEENS1_9allocatorIcEEEE + 191
3 libcoreir.dylib 0x0000000106e4a4dc _ZN6CoreIR12loadFromFileEPNS_7ContextENSt3__112basic_stringIcNS2_11char_traitsIcEENS2_9allocatorIcEEEEPPNS_6ModuleE + 28588
4 coreir 0x0000000106bfacc3 main + 9587
5 libdyld.dylib 0x00007fff610093d5 start + 1
6 ??? 0x0000000000000008 0x0 + 8
Without flatten types, I'm getting:
/Users/durst/anaconda/envs/aetherling/bin/python /Users/durst/dev/W17-8/aetherling/aetherling/examples/ae_circuit24998-6.py
/Users/durst/anaconda/envs/aetherling/lib/python3.7/site-packages/pysmt/walkers/generic.py:43: DeprecationWarning: Using or importing the ABCs from 'collections' instead of from 'collections.abc' is deprecated, and in 3.8 it will stop working
if len(nodetypes) == 1 and isinstance(nodetypes[0], collections.Iterable):
/Users/durst/anaconda/envs/aetherling/lib/python3.7/site-packages/pysmt/walkers/generic.py:43: DeprecationWarning: Using or importing the ABCs from 'collections' instead of from 'collections.abc' is deprecated, and in 3.8 it will stop working
if len(nodetypes) == 1 and isinstance(nodetypes[0], collections.Iterable):
/Users/durst/dev/W17-8/coreir/2coreir/src/binary/coreir.cpp:187 Running Runningvpasses
:114 :10 :26 :114 :114 :114 :114 :114 ERROR: NYI flatten types of generator or nodef module
{global.Term_Tuple_lane_Array_2_Bit__val_Array_50_Array_8_Bit___t}.I Is not a flattened type!
Type is: {'lane':BitIn[2], 'val':BitIn[8][50]}
0 libcoreir.dylib 0x000000010be6d416 _ZN6CoreIR6Passes12FlattenTypes22runOnInstanceGraphNodeERNS_17InstanceGraphNodeE + 278
1 libcoreir.dylib 0x000000010bb602f3 _ZN6CoreIR11PassManager20runInstanceGraphPassEPNS_4PassE + 451
2 libcoreir.dylib 0x000000010bb60983 _ZN6CoreIR11PassManager7runPassEPNS_4PassERNSt3__16vectorINS3_12basic_stringIcNS3_11char_traitsIcEENS3_9allocatorIcEEEENS8_ISA_EEEE + 1075
3 libcoreir.dylib 0x000000010bb622b1 _ZN6CoreIR11PassManager3runERNSt3__16vectorINS1_12basic_stringIcNS1_11char_traitsIcEENS1_9allocatorIcEEEENS6_IS8_EEEESA_ + 1969
4 libcoreir.dylib 0x000000010b9a90b8 _ZN6CoreIR7Context9runPassesENSt3__16vectorINS1_12basic_stringIcNS1_11char_traitsIcEENS1_9allocatorIcEEEENS6_IS8_EEEESA_ + 136
5 coreir 0x000000010b81119c main + 14924
6 libdyld.dylib 0x00007fff610093d5 start + 1
7 ??? 0x0000000000000008 0x0 + 8
Traceback (most recent call last):
File "/Users/durst/dev/W17-8/aetherling/aetherling/examples/ae_circuit24998-6.py", line 135, in <module>
fault_helpers.compile_and_run(tester)
File "/Users/durst/dev/W17-8/aetherling/aetherling/helpers/fault_helpers.py", line 99, in compile_and_run
}, directory="vBuild/", flags=["-Wno-fatal"])
File "/Users/durst/dev/W17-8/fault/fault/tester.py", line 302, in compile_and_run
self._compile_and_run(target=target, **kwargs)
File "/Users/durst/dev/W17-8/fault/fault/tester.py", line 286, in _compile_and_run
self._compile(target, **kwargs)
File "/Users/durst/dev/W17-8/fault/fault/tester.py", line 249, in _compile
self.targets[target] = self.make_target(target, **kwargs)
File "/Users/durst/dev/W17-8/fault/fault/tester.py", line 96, in make_target
return VerilatorTarget(self._circuit, **kwargs)
File "/Users/durst/dev/W17-8/fault/fault/verilator_target.py", line 127, in __init__
Running command: verilator -Wall -Wno-INCABSPATH -Wno-DECLFILENAME -Wno-fatal --cc Module_4.v --exe Module_4_driver.cpp --top-module Module_4
<STDERR>
%Error: Specified --top-module 'Module_4' was not found in design.
%Error: Exiting due to 1 error(s)
%Error: Command Failed /usr/local/Cellar/verilator/4.014/bin/verilator_bin -Wall -Wno-INCABSPATH -Wno-DECLFILENAME -Wno-fatal --cc Module_4.v --exe Module_4_driver.cpp --top-module Module_4
</STDERR>
Found 1 error(s):
1) Got return code 10.
disp_type=self.disp_type)
File "/Users/durst/dev/W17-8/fault/fault/subprocess_run.py", line 142, in subprocess_run
raise AssertionError
AssertionError
Another of my circuits is producing:
λ: double_up_results
Failure with file /private/var/folders/jl/fcct1y6n2tq6drhfnf4f3jdh0000gn/T/ae_circuit36431-378.py
ERROR: In file: vBuild/Module_1.json
Missing typegen symbol coreir.ternary for generator MAD
@rdaly525 how's it going?
The fault related problem here (w.r.t to symbol names) was "fixed" by https://github.com/leonardt/fault/commit/5fa0d4d067241153c599f5bd5d06ea81f770325a#diff-55cb26151ebe14756db3b2683062ceb9 (we now just include all the generated verilator files so we don't need to know specifically how verilate translates the names)
Fixes https://github.com/leonardt/fault/issues/155 but that test is blocked by another issue related to flattening of the commonlib mux (taking out the flatten call results in a generator not being run)