Initial clocks to zero - Githubissues

leonardt / fault

A Python package for testing hardware (part of the magma ecosystem)

BSD 3-Clause "New" or "Revised" License

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Initial clocks to zero #229

Closed leonardt closed 4 years ago

leonardt commented 4 years ago

This has been requested to make things simpler, I don't think it should break any existing code and seems like a reasonable default (rather than using X in SystemVerilog), it also makes verilator/SV consistent.