This adjusts the verilator waveform dumping logic to match the waveforms produced by system verilog (making the generated vcds between the two targets consistent).
Before, verilator was dumping signals in a slightly offset fashion. In system verilog simulators, the vcd will dump the signal values before the clock changes, then the new values on the next tick of the clock. Before this change, the verilator target was dumping signal values after the clock ticked. The new logic dumps the signals before the clock changes, then dumps the clock at the end to handle the final cycle.
The test ensures that verilator and iverilog produce the same timing for the clock signal (this was not the case before these changes).
This adjusts the verilator waveform dumping logic to match the waveforms produced by system verilog (making the generated vcds between the two targets consistent).
Before, verilator was dumping signals in a slightly offset fashion. In system verilog simulators, the vcd will dump the signal values before the clock changes, then the new values on the next tick of the clock. Before this change, the verilator target was dumping signal values after the clock ticked. The new logic dumps the signals before the clock changes, then dumps the clock at the end to handle the final cycle.
The test ensures that verilator and iverilog produce the same timing for the clock signal (this was not the case before these changes).